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61 articles for “Low Power Circuits”
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High Performance Multi-Valued Logic (MVL)Gate Design Using FinFET
Abstract: CMOS scaling faces challenges such as leakage, power dissipation, and short channel effects. Multi-Valued Logic (MVL) offers higher information density and reduced interconnections. This work presents a FinFET-based MVL gate design that improves electrostatic control, switching speed, and reliability. Simulation results confirm reduced leakage power and enhanced performance compared to conventional logic. The proposed architecture demonstrates scalability for advanced technology nodes. It also shows potential for low-power applications in portable …
Published in Journal of Microelectronics and Solid State Devices · Vol. 13, Issue 1, 2026 · pp. 34–45 Read article
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A Comprehensive Review of CMOS Analog Circuit Design Techniques for Low-Power VLSI Systems
Abstract: CMOS analog circuit design plays a significant role in the development of modern low-power Very Large-Scale Integration (VLSI) systems used in wireless communication, biomedical devices, portable electronics, embedded systems, and Internet of Things (IoT) applications. Research on low-power CMOS analogue design methodologies has intensified because to the growing need for high-performance, small, and energy-efficient electronic products. However, reducing power consumption while maintaining signal accuracy, noise performance, stability, bandwidth, and overall …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 4, Issue 1, 2026 Read article
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How small circuits power big technology in the world of VSIL
Abstract: Very Small Integration Level (VSIL) circuit technology represents an emerging class of ultra- compact, low-power electronic design methodologies that enable the creation of highly efficient and scalable systems. This article explores the fundamental principles behind VSIL circuits, including device miniaturization, optimized layout strategies, adaptive power management, and noise-resilient architectures. We also look into the methodical engineering of VSIL circuits to satisfy the ever-tougher performance, robustness, and long- term energy-efficiency demands …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 3, Issue 2, 2025 · pp. 44–53 Read article
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Design of Decoder Using Domino Logic Circuit for VLSI
Abstract: Dissipation of power from a circuit is the major issue in the design of any VLSI circuit, which decreases the life span of a device/system. NMOS and PMOS circuits are very slow while switching the state from low to high. The speed of the circuit can be increased by decreasing resistance. This process in turn increases the static power dissipation. So, because of these disadvantages, CMOS circuits are used in …
Published in Journal of VLSI Design Tools and Technology Read article
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Design and Analysis of Low-Power CMOS Inverter Chains for High-Speed Digital Circuits
Abstract: This report briefly explains the design process, structure, and evaluation of a CMOS inverter designed using a 45 nm technology process with a focus on its propagation delay and power consumption. Moreover, the CMOS inverter design will be created using the Cadence Virtuoso design environment, along with a post-layout analysis of the design. Performance evaluation of the designed circuit will be carried out through the execution of a transient analysis …
Published in Journal of VLSI Design Tools and Technology · Vol. 16, Issue 1, 2026 · pp. 40–57 Read article
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Review And Analysis of Application of Conductive Polymer Composites in Power-Efficient RF Circuits For 5G PAPR Reduction
Abstract: The need for low power RF circuits has gained more importance in the background of fifth-generation (5G) wireless communication systems, since the inherent PAPR characteristic of 5G signals—especially when using orthogonal frequency division multiplexing (OFDM) based techniques—becomes high. This high PAPR limits the efficiency of RF power amplifiers, increases power consumption, and induces thermal management challenges. In this context, conductive polymer composites (CPCs), based on advanced polymer matrices integrated with …
Published in Journal of Polymer & Composites · Vol. 13, Issue 3, 2025 · pp. 111–125 Read article
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Current Controlled Oscillator Using FinFET
Abstract: A current-controlled oscillator using 18 nm FinFET technology is proposed in this study which consists of a Current Controlled Differential Difference Current Conveyor (CCDDCC) block to control the current. FinFET technology has better scalability and lower leakage current compared to traditional CMOS, which allows it to surpass the obstacles faced by CMOS-based oscillators. The suggested oscillator is suitable for electronic applications such as Phase-Locked Loop (PLL) systems, radio frequency (RF) …
Published in Journal of Semiconductor Devices and Circuits · Vol. 12, Issue 3, 2025 · pp. 17–28 Read article
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Design and Implementation of Low-power SPI Shift Register
Abstract: SPI stands for serial peripheral interface which is used for serial, synchronous and full duplex communication of data between master and slave devices. Master devices can be Microprocessors or Microcontrollers; and slaves are the Peripheral devices interfaced with them. The main internal component for architecture of master/slave block is shift register which defines its operation. But as the size of the shift register increases, power is utilized to a greater …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 1, Issue 1, 2023 · pp. 1–15 Read article
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Development of Polymer Based SRAM Cell with Enhance Low Power Performance
Abstract: Low-power memory technologies are in high demand with the rapid growth of portable electronics and energy-efficient computing systems. Static random-access memory (SRAM) plays a crucial role in processors, cache memories, and system-on-chip applications due to their speed and reliability. Static Random Access Memory (SRAM) is typically implemented using complementary MOS (CMOS) technology, which integrates both PMOS (P-channel Metal–Oxide–Semiconductor) and NMOS (N-channel Metal–Oxide–Semiconductor) transistors. However, as technology scales to deep submicron …
Published in Journal of Polymer & Composites · Vol. 14, Issue 1, 2026 · pp. 1439–1448 Read article
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Design and Simulation of Low Power Allow Area High Speed Carry Save Adder using CMOS 16 nm Technology.
Abstract: In this article, we propose a novel 1-bit hybrid full adder circuit that is implemented using eighteen transistors. Simulations are done using the Mentor Graphics Tool 16nm technologies. The performances are evaluated based on their speed, average power consumption, and power-delay product. The essential components of arithmetic units including compressors, comparators, parity checkers, etc. are full adders. Thus, raising the performance of the entire adder will raise the system's performance. …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 1, Issue 2, 2023 · pp. 17–28 Read article
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Design and Simulation of Low-power, High-speed Effective Area Mux Based One-bit Full Adder Using CMOS Technology
Abstract: Our findings reveal a novel kind of circuit capable of performing both XOR and XNOR operations in parallel. Power dissipation and delay are both greatly reduced in the proposed circuits due to their low output capacitance as well as minimal short-circuit power dissipation. We show six new hybrid 1-bit full-adder (FA) circuits that take use of the XOR-XNOR or XOR/XNOR gates' special full-swing function. Each potential circuit layout has both …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 1, Issue 1, 2023 · pp. 25–33 Read article
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Simulation of Adder Circuit Using Reversible Gates in Verilog HDL
Abstract: The emerging field of quantum computing uses quantum logic gates. The reversibility of logic gates is an important aspect of quantum logic gates used in VLSI and quantum computing. Reversibility ensures that power consumption is minimized. This study explores the field of reversible logic and utilizes Peres gate to develop a full adder circuit that shows a significant reduction in power consumption in simulations performed in Xilinx Vivado. We have …
Published in Journal of VLSI Design Tools and Technology · Vol. 14, Issue 3, 2024 · pp. 32–38 Read article
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DFT Compatible Low Power EDAC Based on Clock Gating
Abstract: The in-situ EDAC architecture is normally hired in timing-error tolerant circuits in a try and decrease the conservative timing protect band due to procedure, voltage, and temperature (PVT) fluctuations. But with the addition of the latch-based totally data channel, extra detection, and propagation common sense, it makes the implementation of the layout for- testability (DFT) tough. We present a new low area test overhead DFT EDAC architecture with extreme reduction …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 3, Issue 1, 2025 · pp. 41–53 Read article
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Design and Implementation of High-Speed Low Power Low Area Hybrid One Bit Full Adder Using CMOS Technology
Abstract: In this article, we'll take a look at a new kind of Full Adder (FA) design that mixes traditional Complementary Metal Oxide Semiconductors (CCMOS) with Pass Transistors (PTs) and Transmission Gates (TGs). To analyze the circuit's performance, we used the Mentor Graphics software package. Since all twenty (20) varieties of Full Adder circuits were able to be measured and compared, this research was conducted. When the clock rate of the …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 1, Issue 2, 2023 · pp. 29–39 Read article
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Design and Simulation of LNA in 90 nm CMOS Technology for Radio Receiver using the Cadence Simulation Tool
Abstract: Due to its successful operation in the 2.4 GHz frequency region, often known as the ISM (Industrial, Scientific, and Medical) band, RFICs play a vital role in communication systems. The major parts being used transceivers for frequency translation and amplification are LNA and Mixers. Different types of mixers and LNAs are employed, and different strategies are used to optimize them. In this paper an approach for design and simulation of …
Published in International Journal of Digital Communication and Analog Signals Read article
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A Comprehensive Review of FinFet Technology: Advantages, Challenges and Applications
Abstract: This has been complemented by improvements on the new layers that have surpassed the manufactures planar transistor by the new FinFET (Fin Field-Effect Transistor), which enhance modern demands on high performance, small size and low power consumption. This review is for a timely information on the latest development on FinFET technology, such as by curbing leakage currents by 50 percent and enhancing its speed by 30 percent proving that FinFETs …
Published in Journal of Semiconductor Devices and Circuits · Vol. 11, Issue 3, 2024 · pp. 1–12 Read article
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A study on CMOS Operational Amplifier in Sensor Development
Abstract: CMOS operational amplifiers (op-amps) have emerged as pivotal components in modern sensor development, enabling the amplification and conditioning of weak signals with high precision and efficiency. Their inherent advantages low power consumption, compact size, and seamless integration with digital circuits make them ideal for advancing miniaturized, battery-powered sensor systems in fields ranging from biomedical devices to IoT networks. By delivering precision, power efficiency, and integration, CMOS op-amps are not just …
Published in Journal of VLSI Design Tools and Technology · Vol. 16, Issue 1, 2026 · pp. 01–07 Read article
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High-speed Data Converter Architectures: Latched Comparator Design & Performance Comparison
Abstract: This paper focuses on the design and optimization of latch comparators for high-speed data converter applications. The performance of different comparator architectures is compared in terms of speed, power consumption, and noise performance. The proposed latch comparator architecture uses a preamplifier to boost gain and sensitivity, and a latch to store the output signal. The latch comparator design is optimized for low power consumption and high speed, and is implemented …
Published in Journal of VLSI Design Tools and Technology · Vol. 14, Issue 1, 2024 · pp. 23–32 Read article
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A Majority Function Based Full Subtractor
Abstract: In the present landscape of very large-scale integration (VLSI) technology, the imperative to implement Boolean functions with minimal gate count remains a cornerstone of efficient circuit design. This pursuit has only grown more critical with the evolution of low-power design strategies, which now offer significantly enhanced benefits compared to traditional approaches. The trifecta of performance, affordability, and dependability continue to drive innovation in this field, shaping the trajectory of technological …
Published in Research & Reviews : Journal of Physics · Vol. 13, Issue 2, 2024 · pp. 8–14 Read article
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Design of Optimized Full Adder using Noise-Mitigation Techniques and Power Gating
Abstract: With the advent of nanoscale technology, a new era of power consumption, speed, and reliability challenges for traditional static CMOS logic has begun. To solve these problems, dynamic logic families—particularly domino logic—have emerged as potent substitutes that offer quicker processing speeds and lower power consumption. The design and optimization of a full adder circuit using domino logic is shown in this study. A dynamic domino logic technique is used to …
Published in Journal of Microelectronics and Solid State Devices · Vol. 11, Issue 3, 2024 · pp. 1–6 Read article