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85 articles for “Clock”
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Performance Analysis and Characterization of Shared Charge and Clocked-Latch based Comparator using 90-nm Technology
Abstract: Paper describes the performance analysis, implementation and characterization of low-power and high-speed shared charge clocked-latch based comparator using 90-nm technology. There are two different topologies of the comparator viz. impedance dividing and differential current sensing comparators are combined to take the advantages and use their good features. The main focus of design is on improvement in speed by sharing charge and reduction in power dissipation. The topology is implemented in …
Published in Journal of VLSI Design Tools and Technology · Vol. 4, Issue 3, 2014 · pp. 20–26 Read article
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Design of Slew Aware Clock Distribution Network for Ultra Low Power Sub-threshold Applications
Abstract: Clock distribution network consumes significant amount of power due to its high switching activity. The high power consumption issue can be satisfactorily addressed by the sub-threshold operation of device, however at the cost of degraded performance and magnified variability. This paper investigates the suitability of conventional clock distribution network for sub-threshold regime and proposes a novel strategy of having an optimized uniform H-tree with a pair of buffer only at …
Published in Journal of VLSI Design Tools and Technology · Vol. 9, Issue 1, 2019 · pp. 22–37 Read article
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Design of Energy Efficient Clock System
Abstract: Energy efficiency is a key metric for energy constrained Ultra Low Power (ULP) VLSI applications such as wireless sensor nodes, pace makers, hearing aids etc. These applications need clock system in their signal processing and communication sub-system. Moreover, clock system plays a vital role in governing the reliability, power consumption and performance of synchronous system. In today’s era of portable electronics, power consumption has emerged as a forefront design metrics. …
Published in Journal of VLSI Design Tools and Technology · Vol. 9, Issue 2, 2019 · pp. 1–7 Read article
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The Doomsday Clock and Global Health: A Medical Sociological Analysis of Existential Threats to Human Civilization From 1947 to 85 Seconds to Midnight Situating the Biosocial Crises of the Twenty-First Century
Abstract: Since its inception in 1947, the Doomsday Clock maintained by the Bulletin of the Atomic Scientists has functioned as a socially constructed barometer of civilisational risk, translating complex scientific, geopolitical, and technological threats into a universally legible symbolic chronometry. As of January 2026, the Clock stands at 85 seconds to midnight, its most alarming position in nearly eight decades of operation. This article adopts a medical sociological framework, drawing on …
Published in Recent Trends in Social Studies · Vol. 3, Issue 2, 2026 · pp. 26–36 Read article
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A Precise Clock Synchronization Algorithm in Network
Abstract: To execute a task in a synchronized manner in a distributed setting, we need the common idea of time. To accomplish this intention, clock synchronization is conceptualized. Clock drifting is an intrinsic property of a clock, which necessitates the synchronization. A network consists of nodes, which may execute appropriately or behave badly. The mischievous node may pose difficulty in clock synchronization. We require a method to ease the effect of …
Published in Journal of Communication Engineering & Systems · Vol. 10, Issue 1, 2020 · pp. 12–21 Read article
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Comparison between First and Second Stage of Clock Drivers Using 65 nm PTM
Abstract: The paper is composed of generally two parts. The first part basically deals with the designing of clock distribution network for a branch-2 tree, also a wire model for 1 mm wire and designing a clock distribution network using wires and inverter pairs (buffers) to distribute a clock to the loads. Keeping this in to account simulation is analyzed and evaluated the results. The second part is to designing a …
Published in Journal of Microcontroller Engineering and Applications · Vol. 3, Issue 1, 2016 · pp. 10–15 Read article
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Efficient Analysis and Minimization of Glitches using Threshold Swapped Combinational Clock Gating
Abstract: Nowadays design of electronic circuits to meet requirements like high speed, better functionality and low power is a tedious task. Power dissipation in any circuit comprises mainly two components: static power and dynamic power. The dynamic power heavily depends on the switching activity of the circuit. During the transistor switching transitions some spikes may occur, which are called as glitches. These glitches contribute 20–70% of the dynamic power and 20% …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 2, 2015 · pp. 29–37 Read article
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RTL-to-GDSII Flow Optimization for Low-Power 32-bit RISC-V Processor
Abstract: This paper presents the implementation and optimization of a 32-bit RISC-V processor, transitioning from Register Transfer Level (RTL) design to final GDSII using Synopsys Fusion Compiler over 32nm technology node. The processor architecture is based on the RV32I base instruction set and incorporates a 5-stage pipeline to achieve a balanced trade-off between performance and design complexity. The design methodology involved RTL synthesis, gate-level netlist generation, and successive physical design stages …
Published in Journal of VLSI Design Tools and Technology · Vol. 15, Issue 3, 2025 · pp. 1–10 Read article
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Comparative Study of a 32 bit Clock Gated ALU based on Carry Skip Adder and Ripple Carry Adder
Abstract: The ALU is one of the most frequently accessed modules in a CPU and is utilized during most instruction executions. Hence the power consumption of the ALU is a major concern. In this paper a low power 32 bit ALU is designed using VHDL. Lower power consumption is achieved by using clock gating technique than conventional design. A carry skip adder with variable block length is used for the arithmetic …
Published in Journal of VLSI Design Tools and Technology · Vol. 3, Issue 2, 2013 · pp. 6–11 Read article
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DFT Compatible Low Power EDAC Based on Clock Gating
Abstract: The in-situ EDAC architecture is normally hired in timing-error tolerant circuits in a try and decrease the conservative timing protect band due to procedure, voltage, and temperature (PVT) fluctuations. But with the addition of the latch-based totally data channel, extra detection, and propagation common sense, it makes the implementation of the layout for- testability (DFT) tough. We present a new low area test overhead DFT EDAC architecture with extreme reduction …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 3, Issue 1, 2025 · pp. 41–53 Read article
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Review of Low Power Johnson Counter
Abstract: Due to the use of clock gating the authors have achieved a power reduction of 37.12 to 41.08% for different frequencies. The authors have run T-Spice simulations for conventional design and clock-gated Johnson counter design. There is a huge difference in the power consumption of the two designs. The clock-gating logic gives this change. And as a 2-input flip-flop is used instead of 3-input flip-flop plays a remarkable role in …
Published in Journal of Microelectronics and Solid State Devices · Vol. 2, Issue 1, 2015 · pp. 13–17 Read article
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Role of ion Regulation in Heartbeat Initiation
Abstract: The heart can beat quite 2 billion times in normal life, but the mechanism by which the guts beats is that the subject of intense research. Since the invention of pacemaker currents in 1978, several studies have shown that rhythmic changes in membrane tension (the "membrane tension clock") underlie the mechanism of automation. It's the depolarizing current activated during hyperpolarization. Therefore, when the guts cells recover, it's activated, the cell …
Published in Research and Reviews: A Journal of Medicine Read article
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Role of ion Regulation in Heartbeat Initiation
Abstract: The heart can beat quite 2 billion times in normal life, but the mechanism by which the guts beats is that the subject of intense research. Since the invention of pacemaker currents in 1978, several studies have shown that rhythmic changes in membrane tension (the "membrane tension clock") underlie the mechanism of automation. It's the depolarizing current activated during hyperpolarization. Therefore, when the guts cells recover, it's activated, the cell …
Published in Research and Reviews: A Journal of Medicine · Vol. 12, Issue 3, 2022 · pp. 1–6 Read article
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Design of Optimized Full Adder using Noise-Mitigation Techniques and Power Gating
Abstract: With the advent of nanoscale technology, a new era of power consumption, speed, and reliability challenges for traditional static CMOS logic has begun. To solve these problems, dynamic logic families—particularly domino logic—have emerged as potent substitutes that offer quicker processing speeds and lower power consumption. The design and optimization of a full adder circuit using domino logic is shown in this study. A dynamic domino logic technique is used to …
Published in Journal of Microelectronics and Solid State Devices · Vol. 11, Issue 3, 2024 · pp. 1–6 Read article
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Revolutionizing School Schedules: An Arduino-Based Automatic Class Bell System with Real-Time Precision
Abstract: A sound that evokes nostalgia, signals transitions, and dictates the rhythm of academic life. However,the traditional reliance on manual bell ringing is prone to human error, inconsistencies, and inflexibility. This work explores the design and implementation of an Arduino-based automatic class bell system leveraging a Real-Time Clock (RTC) module to provide accurate and reliable bell timing. This system offers a significant upgrade over manual systems, streamlining school schedules and improving …
Published in Journal of Control & Instrumentation · Vol. 16, Issue 2, 2025 · pp. 35–44 Read article
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Study and Analysis of Digital Counters for VLSI Applications
Abstract: AbstractThe counter is a fundamental and essential component. It is used in most digital devices. A counter is a sequential circuit that is used as a counter. The counter is the most widespread application of flip-flops. It is a group of flip-flops in which a clock signal is placed. A counter stores the number of processes related to a clock. It is classified into two categories. The number of flip-flops …
Published in Recent Trends in Programming languages · Vol. 7, Issue 3, 2020 · pp. 17–24 Read article
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Advanced Energy Metering and Automated Control System
Abstract: In this paper need for energy efficiency especially combining smart metering with control of load and prepaid billing becomes insistent. An ESP32-based Advanced Energy Metering and Automated Load Control System, is presented in this paper taking advantage of an IoT-capable smart meters, real-time data analytics, motion detector-based automation scheduling, Real-time clock (RTC) module-enabled scheduling, and GSM based prepaid billing notifications. The central controller, responsible for real-time energy monitoring, automated load …
Published in Journal of Control & Instrumentation · Vol. 17, Issue 2, 2026 · pp. 8–15 Read article
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IoT Operated Pillbox for Old Age Persons to Remember the Medicines Dosages
Abstract: In today's fast-paced world, remembering to take medications on time can be a real challenge. Missing doses can have serious consequences for health and well-being. To combat this issue, we can leverage the power of Internet of Things (IoT) to create a smart pill box that ensures timely medication adherence. This study will guide researchers through building a simple yet effective IoT-operated pill box using an Arduino Nano, a buzzer, …
Published in Journal of Microelectronics and Solid State Devices · Vol. 12, Issue 2, 2025 · pp. 20–32 Read article
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Implementation of Sense Amplifier-based D Flip-Flop using 0.25 µm and 0.18 µm Technology
Abstract: The traditional flip-flops and latches suffer from the large delays and the race conditions. This paper describes a new approach to the D flip-flop design using the sense amplifier. The previous efforts in the same direction made at the 0.25 µm technology exhibit improvements in clock-to-output delay and power dissipation with respect to recently proposed high-speed flip-flops. The paper discusses the flip-flop at 0.18 µm technology. The output latch of …
Published in Journal of Electronic Design Technology · Vol. 4, Issue 3, 2013 · pp. 10–13 Read article
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True Random Number Generators Using A Postprocessor, Jitter Metastability, Tree-based Interleaver & Low-power CMOS inverter Circuit prototype technology: An Efficient Analysis
Abstract: TRNGs (True Random Number Generators) are cryptographic primitives that generate random numbers for critical operations. The goal of this study is to create a TRNG using a ring oscillator, analyse different calibration generating ways using VHDL spice simulation, and investigate the TRNG's essential design features, such as area, entropy, and power/energy consumption, using suggested and published methods. Random ones and zeros are produced using RO jitter and DCM frequency fluctuations. …
Published in Journal of Microcontroller Engineering and Applications · Vol. 10, Issue 1, 2023 · pp. 66–76 Read article