The paper is composed of generally two parts. The first part basically deals with the designing of clock distribution network for a branch-2 tree, also a wire model for 1 mm wire and designing a clock distribution network using wires and inverter pairs (buffers) to distribute a clock to the loads. Keeping this in to account simulation is analyzed and evaluated the results. The second part is to designing a two-stage clock driver considering that first stage has the minimum size transistors and simulating the output of the level 1 of node 5 in Figure 2 at frequency of 500 MHz.Keywords: Clock Driver, Clock Distribution, Transistors Sizing, PTMCite this ArticleHerman-Al-Ayubi, Navaid Z. Rizvi. Comparison between First and Second Stage of Clock Drivers Using 65 nm PTM. Journal of Microcontroller Engineering and Applications. 2016; 3(1): 10–15p.
