STM Journals Peer-reviewed research from Consortium e-Learning Network

Journal of Microelectronics and Solid State Devices

Review of Low Power Johnson Counter

  1. Himanjali Agarwal
  2. Himani Mittal
  3. Gayatri Sakya

Abstract

Due to the use of clock gating the authors have achieved a power reduction of 37.12 to 41.08% for different frequencies. The authors have run T-Spice simulations for conventional design and clock-gated Johnson counter design. There is a huge difference in the power consumption of the two designs. The clock-gating logic gives this change. And as a 2-input flip-flop is used instead of 3-input flip-flop plays a remarkable role in power loss minimization. There is reduction in power in comparison to conventional design but clock-gating logic being the additional circuitry has its own power dissipation. But after including this power dissipation also, there is decrease in average power consumption. Future work would include more reduction of power dissipation of clock-gating logic.
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