Journal of Microelectronics and Solid State Devices
Volume 2, Issue 1 (2015)
Published
Table of contents
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Test Pattern Generator for Built-in Self-test
Abstract: Low power BIST implementation is the need of the hour as testing is the most power-consuming process of chip operations. The power consumed during testing is almost twice as the power consumed during normal circuit operation. This paper gives the comparative analysis of power consumed by an improvised LFSR on two devices under test. The research also gives a decrease in number of logic gates in the circuit which is …
Published in Journal of Microelectronics and Solid State Devices · Vol. 2, Issue 1, 2015 · pp. 1–5 Read article
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Review of Low Power Johnson Counter
Abstract: Due to the use of clock gating the authors have achieved a power reduction of 37.12 to 41.08% for different frequencies. The authors have run T-Spice simulations for conventional design and clock-gated Johnson counter design. There is a huge difference in the power consumption of the two designs. The clock-gating logic gives this change. And as a 2-input flip-flop is used instead of 3-input flip-flop plays a remarkable role in …
Published in Journal of Microelectronics and Solid State Devices · Vol. 2, Issue 1, 2015 · pp. 13–17 Read article
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Built in Self Repair for Embedded Memories: A Survey
Abstract: Memory is a significant part of every single computing system. In SOC (System-on-a-chip), 90 to 92% of the total chip zone is enclosed by embedded memories (ITRS 2009) and that means memory density is higher than the logic density. Consequently testing and diagnosis of memories are imperative issues in the SOCs. Revenue of memory is pretentious by the accountabilities present in memory which also distresses the yield of SOC. Built …
Published in Journal of Microelectronics and Solid State Devices · Vol. 2, Issue 1, 2015 · pp. 18–22 Read article
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Implementation of UART with CALBO
Abstract: The increasing growth of submicron technology has resulted in the difficulty of VLSI testing for designers who always look for simple and cost effective logic structure to realize a complex function. Thus Automatic Testing Equipment (ATE) is becoming costly process for testing. To reduce the cost of testing the chips, Built in Self-Test (BIST) has emerged as a cheaper alternative. BIST is a design technique that allows the chip to …
Published in Journal of Microelectronics and Solid State Devices · Vol. 2, Issue 1, 2015 · pp. 6–12 Read article