STM Journals Peer-reviewed research from Consortium e-Learning Network

Journal of Microelectronics and Solid State Devices

Implementation of UART with CALBO

  1. Nishtha Singh
  2. Sangeeta Mangesh

Abstract

The increasing growth of submicron technology has resulted in the difficulty of VLSI testing for designers who always look for simple and cost effective logic structure to realize a complex function. Thus Automatic Testing Equipment (ATE) is becoming costly process for testing. To reduce the cost of testing the chips, Built in Self-Test (BIST) has emerged as a cheaper alternative. BIST is a design technique that allows the chip to test itself. Several architectures are used for implementing BIST. In this paper, the BIST is implemented using CALBO architecture on UART using Verilog. The simulation and synthesis of the design are performed using ModelSim SE PLUS 6.5 simulator and XILINX ISE 14.5 synthesis tool
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