STM Journals Peer-reviewed research from Consortium e-Learning Network

Journal of Microelectronics and Solid State Devices

Test Pattern Generator for Built-in Self-test

  1. Gargi Kaushik
  2. Sangeeta Mangesh

Abstract

Low power BIST implementation is the need of the hour as testing is the most power-consuming process of chip operations. The power consumed during testing is almost twice as the power consumed during normal circuit operation. This paper gives the comparative analysis of power consumed by an improvised LFSR on two devices under test. The research also gives a decrease in number of logic gates in the circuit which is advantageous. For simulation, Modelsim is used, for power calculation we use QUARTUS II 13.1.
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