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• Published Subscription 2 Feb 2021

  Review of Low Power Johnson Counter

  By Himanjali Agarwal, Himani Mittal, Gayatri Sakya

  Abstract: Due to the use of clock gating the authors have achieved a power reduction of 37.12 to 41.08% for different frequencies. The authors have run T-Spice simulations for conventional design and clock-gated Johnson counter design. There is a huge difference in the power consumption of the two designs. The clock-gating logic gives this change. And as a 2-input flip-flop is used instead of 3-input flip-flop plays a remarkable role in …

  Published in Journal of Microelectronics and Solid State Devices · Vol. 2, Issue 1, 2015 · pp. 13–17 Read article →