Search results for “IEEE 802.15.4 standard”

Published Subscription 26 Jul 2023

Standard for Exchange of Products (STEP) based feature Recognition System for Prismatic Parts

By VIJAY PANDEY

Abstract: Feature extraction is considered as the bridge between Computer Aided Design (CAD) and Computer Aided Process Planning (CAPP). This work is concerned with understanding the problem of how to manipulate and extract information from CAD solid models by using Standard for Exchange of Product data model (STEP) files and its further use in downstream manufacturing operations. Emphasis is placed on recognizing and classifying manufacturing features from the Boundary Representation (BREP) …

Published in Journal of Production Research & Management · Vol. 1, Issue 1-2-3, 2011 · pp. 73–91 Read article

Published Subscription 25 Jan 2021

VLSI Implementation of Bit/Digit Serial-Parallel Finite Field GF (2m) Multiplier Using Standard Basis

By M. Manasa, K. Saujanya

Abstract: A Finite Field is a field with finitely number of elements. It is also known as Galois field in which the elements can take q different values is referred as GF (q).Finite fields are of great interest in applications like Elliptic Curve Cryptography (ECC), error control and coding. In this paper, we present a simple implementation of finite field GF (2m) multiplier. Here the main aim is to enhance the …

Published in Journal of Semiconductor Devices and Circuits · Vol. 1, Issue 3, 2014 · pp. 1–6 Read article

Published Subscription 27 Dec 2017

Performance Analysis of 3T DRAM Using FinFET Based with Leakage Reduction Techniques at 45 nm Technology

By Bharat Tripathi, Saurabh Khandelwal

Abstract: The proposed area of research is to reduce the power consumption, leakage voltage, leakage current and leakage power of DRAM while maintaining the competitive performance. The Fin FET approach is used in DRAM for high performance. Fin type field effect transistors (Fin FET) are capable substitutes for bulk CMOS at the nano-scale. Fin FET are double gate device. A Fin FET uses an intrinsic body. It greatly suppresses the device-performance …

Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 3, 2017 · pp. 28–34 Read article

Published Subscription 19 Jul 2019

A Novel 4:1 Multiplexer Design using Power Minimization Technique based Domino Logic

By Vignesh M, Naveen R

Abstract: Domino circuits are widely used these days in the design of modern-day microprocessors because of their high speed and less area overhead compared to static logic style. In this paper, a new domino-based 4:1 multiplexer circuit has been designed which finds extensive use in register files and execution units where large amounts of data have to be broken into smaller chunks so that the processor can manipulate it more easily …

Published in Journal of VLSI Design Tools and Technology · Vol. 3, Issue 3, 2013 Read article

Published Subscription 8 Aug 2019

Design and Implementation of 2nd Order Gm-C IF Tuning Filter Operating at 900 MHz and 88–108 MHz Wireless System for Multi Standard Receiver

By Kehul A. Shah, N M Devashrayee

Abstract: This paper deals with design and optimization of folded cascode OTA-C filter, which works for frequencies that lead to a base band circuit design for RF application, is based on transistor sizing methodology and Simulation results are performed using SPICE software and BSIM3V3 model for CMOS 0.18 μm process, show that the designed folded cascode OTA has a 52 dB DC gain and provides a Unit gain bandwidth of around …

Published in Journal of VLSI Design Tools and Technology · Vol. 4, Issue 1, 2014 · pp. 8–24 Read article

Published Subscription 25 Nov 2021

A Nobel Approach of Designing A 4 Bit Carry Skip Adder Using Reversible Logic

By Pinaki Satpathy, Santanu Maity

Abstract: This paper presents a method to designing Various Adder Circuits using CMOS Logic Style for Energy-Efficient Arithmetic Applications. We present Ripple Carry Adder, Carry Bypass Adder, Carry Look Ahead Adder and Carry Skip Adder in CMOS logic styles that lead to have reduced power-delay product (PDP). We executes a comparison against each other adders which finally provide result as having a low PDP, with reference to power consumption, speed and …

Published in Journal of VLSI Design Tools and Technology · Vol. 11, Issue 2, 2021 · pp. 24–34 Read article

Published Subscription 11 Dec 2020

Standardization of Cement Mortar by Using GGBS for Plaster Work

By Priyanka Sabale, Vrushali Tandulkar, Snehal Randive, Gaurav Mishra, Omkar Sherkar, Deepak Chavan, Milinda Mahajan, Archana Tanawade

Abstract: This study investigates the feasibility of using replacement of natural river sand with 100% crushed sand, and partial replacement of cement with optimum percentage of ground granulated blast furnace slag (GGBS) on site conditions with a proportioned water cement ratio for plaster work. The methodology, which it undergoes, is slump test, compressive strength, flexural strength, split tensile strength. Cubes (70.6 mm  70.6 mm), beams (160 mm  40 mm), …

Published in Recent Trends in Civil Engineering & Technology · Vol. 6, Issue 2, 2016 · pp. 23–29 Read article

Published Subscription 16 Aug 2019

Finding The Most Sensitive Nodes on IEEE-14 Bus System and Adaptation of Protection Scheme

By M S Muhit, raihan miah, rafiqul islam, osman bin ashraf

Abstract: Power system stability is one of the most significant concerns in power system. Providing continuous supply of electric energy to meet the load demand is a complex technical challenge. One of the main causes of voltage instability in a system is the occurrence of reactive power imbalance in the system. Reactive power will be unbalanced when there is a sudden increase or decrease in reactive power demand in the system. …

Published in Trends in Electrical Engineering · Vol. 6, Issue 1, 2016 · pp. 50–56 Read article

Published Subscription 30 Mar 2019

Performance Study in Modified DPSK, MZI Delay Mismatch at 40Gbps Fiber Dispersive Channel

By Devendra Kr. Tripathi

Abstract: AbstractHigher data rate transmission is a desirable feature for the communication system in every era. As they have potentially higher fiber capacity, also have lower cost per bit. This paper presents performance investigation with partial differential phase shift keying and influence of MZI delay mismatch in the high data rate dispersive channels. Ideal fiber braggs grating is considered as fiber dispersive medium with different dispersion. Numerical simulation depicts that in …

Published in Trends in Opto-electro & Optical Communication · Vol. 6, Issue 2, 2016 · pp. 18–23 Read article