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156 articles for “gating design”
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Implementation of Optical XOR Gate and Gray to Binary Code Converter Using Mach-Zehnder Interferometer
Abstract: AbstractWith the progress in optical communication system, optical networks are demanding of all optical devices to improve the speed, power and to reduce the attenuation during transmission of signals. In this paper, execution of gray to binary code converter with the aid of semiconductor optical amplifier (SOA) based Mach-Zehnder interferometer (MZI) is proposed, with the help of all-optical XOR logic gate, which is also demonstrated by using SOA-MZI, where CW …
Published in Trends in Opto-electro & Optical Communication · Vol. 7, Issue 1, 2017 · pp. 1–5 Read article
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Design and Implementation of Low Power Priority Encoder
Abstract: Nowadays, low-power devices are widely used in VLSI design technology because they can reduce power consumption and power dissipation. To achieve this, various low-power techniques are utilized to minimize device power losses. This project focuses on analyzing the performance of priority encoders in different low-power technologies for Flash Type ADC. Moreover, the power consumption of these technologies is compared with the conventional CMOS design. Each of these techniques offers distinct …
Published in Journal of Microcontroller Engineering and Applications · Vol. 10, Issue 2, 2023 · pp. 1–14 Read article
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Study the Effect of Applied Gate Voltage on Threshold Potential and Carrier Transport Behavior of Three-Terminal Novel Prototype Device having Configuration P-type Si/SiO2/CuFeS2/Al
Abstract: This study presents a trial approach for the fabrication and characterization of a novel p-Si/SiO₂/CuFeS₂/Al field-dependent three-terminal electronic device designed to investigate charge transport behavior across multiple semiconductor junctions under externally applied bias voltages. The proposed prototype incorporates CuFeS₂ (chalcopyrite) as the active semiconductor layer, marking its first reported application in a field-induced electronic device architecture. The device was fabricated using a layered heterostructure consisting of p-type silicon, a silicon …
Published in International Journal of Crystalline Materials · Vol. 3, Issue 2, 2026 · pp. 1–7 Read article
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Performance Comparison of Noise-Tolerant, High- Performance CMOS Domino Logic Configurations
Abstract: In high-performance VLSI chip design, domino logic configuration is often preferred over static logic due to its faster operation and smaller area footprint, especially in deep submicron (DSM) technology. However, DSM noise has become a significant challenge in domino-based circuits, leading to compromises in the reliability and signal integrity of integrated circuits (ICs). The switching threshold of domino logic, defined as the input voltage level at which the gate output …
Published in Journal of Semiconductor Devices and Circuits · Vol. 12, Issue 2, 2025 · pp. 35–50 Read article
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A Review on Home Automation System using IoT
Abstract: The theme of this IoT-based Home Automation System is to create a smarter, safer, and more energy-efficient living environment by integrating modern sensing and communication technologies. Convenience and time management have become vital components of daily living in today's fast-paced society. The growing demand for intelligent living has encouraged the adoption of technologies that automate everyday activities, strengthen residential security, and improve the efficient utilization of energy resources. Home automation …
Published in International Journal of Electrical Machine Analysis and Design · Vol. 4, Issue 2, 2026 Read article
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Suitability of Various Low Power Strategies for SRAM Design: A Survey
Abstract: In very high performance system on chip, static power dissipation plays a dominant role compared to dynamic component and it increases with technology scaling. Scaling of bulk MOSFET faces more and more challenges at 45 nm technology or below by producing short channel effect (SCE) which leads to increase in leakage current. An obstacle with bulk MOSFET at 45 nm or below gate length includes SCE, subthreshold leakage and gate …
Published in Journal of Semiconductor Devices and Circuits · Vol. 2, Issue 1, 2015 · pp. 6–13 Read article
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IoT-Enabled Remote Patient Monitoring System Using Wearable Sensors
Abstract: In recent years, the Internet of Things (IoT) has revolutionized healthcare by enabling seamless connectivity between patients, medical devices, and healthcare professionals. The increasing demand for continuous health monitoring and early disease detection has driven the development of IoT-based remote patient monitoring systems. This paper presents an IoT-enabled framework that integrates wearable physiological sensors, wireless communication modules, and cloud- based analytics to facilitate real-time health tracking. The proposed system continuously …
Published in Recent Trends in Electronics Communication Systems · Vol. 13, Issue 1, 2026 · pp. 1–14 Read article
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Coarse-grained Logic Interface with Floating-point Arithmetic Unit: A Review
Abstract: One of the key elements of their design, which has a substantial impact, is their choice of programmable connectivity and logic capabilities. The FPGA architecture has a significant impact on the speed performance, space efficiency, and power consumption of the finished device. This examination examines the evolution of programmable logic devices over time, the underlying programming paradigms that underpin programmability, and the most important findings from architectural system research. We …
Published in Research & Reviews: A Journal of Embedded System & Applications · Vol. 11, Issue 2, 2023 · pp. 18–24 Read article
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Which is the Best 10T Static CMOS Full Adder for Ultralow-Power Applications?
Abstract: This paper presents the analysis of various 10-transistor CMOS 1-bit full adder circuits in terms of their output levels and finds out the suitable adder cell at 200 mV in subthreshold region at 16-nm technology node for ultra-low power applications. This paper also provides worst case output levels (sum and carry) of all the analyzed adder cells (which are presented in the paper) for various input combinations.Keywords: CMOS, carry, 2:1 …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 1, 2015 · pp. 45–50 Read article
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Time Domain Analysis in an On-chip High Speed RLCG Interconnection Network at 0.18 µm Technology
Abstract: In this model, the time domain waveform is evaluated for calculation of delay time, peak time, settling time, damping ratio and natural frequency for a second order RLCG interconnect network. It can also be used for multiple interconnect systems but for higher order systems it is ignored due to accurate analysis. The model is applied to a single resistance-inductance-capacitance-conductance model which can also be extended to multi-interconnect systems to analyze …
Published in Journal of VLSI Design Tools and Technology · Vol. 1, Issue 1-2-3, 2011 · pp. 57–67 Read article
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Advanced Mathematical Modelling of Nanoscale Semiconductor Devices for Low-Power Microelectronic Applications
Abstract: With the ongoing scaling down of semiconductor devices, there is an increasing need for accurate mathematical models of electrostatic control, carrier transport, leakage current, and power consumption at the nanometer scale. As the sizes of semiconductors continue to decrease, there is a growing need for accurate mathematical models of electrostatic control, carrier transport, leakage current, and power consumption at the nanometer scale. In this work, a common mathematical modelling approach …
Published in Journal of Microelectronics and Solid State Devices · Vol. 13, Issue 2, 2026 Read article
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Virtual Tooling Development and Tooling Cost Estimation for Sand Casting
Abstract: Casting is a major manufacturing process. It requires an understanding of a wide range of geometrical, material and process parameters. For producing cost effective casting, in today's market of intense competition, where the need of the hour is to develop quality products at low cost and short lead time, innovative and cost effective designs are the means to success. Early cost estimation, necessary for design-to-cost philosophy, serves as a decision …
Published in Trends in Mechanical Engineering & Technology · Vol. 7, Issue 3, 2017 · pp. 59–66 Read article
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FPGA Enabled Flight Control Unit
Abstract: The FPGA flight controller revolutionizes drone technology with unmatched stability and precision. Integrated with an IMU and advanced sensors like the MPU 6050, it ensures accurate positioning critical for reliable UAV operation. Its efficient real-time data processing and seamless sensor communication enhance performance and reliability across various conditions. This advancement sets a new standard in UAV technology, suitable for applications ranging from surveillance to disaster relief. An aircraft's flight control …
Published in Journal of Aerospace Engineering & Technology · Vol. 14, Issue 1, 2024 · pp. 19–25 Read article
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Implementation of Edge Detection Algorithm on FPGA using Hardware Software Co-simulation
Abstract: Image processing is one of the most booming research areas in modern days. Every modern device incorporates image processing in one or the other way. Most of the image processing algorithms start with basic edge detection. The performance of the edge detection can be improved using state of art FPGA devices. Implementation using field programmable gate arrays (FPGA) speeds up the processing of edge detection algorithms. The paper discusses the …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 1, 2016 · pp. 55–61 Read article
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Effect of Various Parameters on Threshold Voltage of Virtually Fabricated Lightly Doped PMOS Device
Abstract: This paper emphasis on the design, fabrication and analysis of 45 nm P type MOSFET device using SILVACO TCAD tool. The analysis was based on variation of various parameters like oxide thickness, threshold implant and halo implant (pockets) to analyze the threshold voltage. The drain versus gate and drain versus gate plots are being plotted using tony-plot. It has been observed that as the thickness of the oxide increases, threshold …
Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 3, 2017 · pp. 13–20 Read article
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Numerical Simulation-based Comparative Study of P3HT-based Top Contact and Bottom Contact OTFTs
Abstract: AbstractIn this paper presents numerical simulation-based comparative study of bottom and top contact configurations of P3HT based organic thin-film transistor (OTFT). I-V characteristics has been evaluated using the TCAD simulator and comparison of the performance parameters of these devices has been presented. The dimensions of the transistors for all the proposed structures are kept the same for a valid comparison between them. The observed results were explained based on the …
Published in Journal of Electronic Design Technology · Vol. 10, Issue 3, 2019 · pp. 27–32 Read article
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High Speed and Low Area Energy Efficient FPGA Implementation using RSD based Elliptic Curve Cryptography
Abstract: In this paper we will study high speed energy efficient FPGA implementation using redundant sign digit elliptic curve cryptography. In existing system to design processor with high area and low speed computation process so that we proposed to low area with high speed computation using Elliptical cryptography processor. Here we use redundant signed digit to reduce the overhead due to computations. For modular arithmetic operation for multiplication, we used Karatsuba-Ofman …
Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 3, 2017 · pp. 45–50 Read article
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Design and Implementation of an Online Food Ordering System
Abstract: This study illustrates how the Online Food Ordering System has been tailored specifically to address the operational needs of Hotel Ambika, a semi-urban establishment. The system is designed to offer customers a smooth and interactive experience, allowing them to navigate through an organized menu, personalize their orders, and complete transactions with minimal effort. By using secure payment gateways and a virtual cart for easy order management, the system ensures a …
Published in Journal of Computer Technology & Applications · Vol. 16, Issue 2, 2025 · pp. 106–115 Read article
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Optimized Hardware Realization of AES for High-Throughput FPGA Platforms
Abstract: The Advanced Encryption Standard (AES) is the predominant symmetric-key cryptographic algorithm used for securing digital communication across embedded systems, IoT devices, cloud infrastructures, and defense networks. Although software-based AES implementations offer flexibility, they often fail to meet the high-speed, low-latency, and energy-efficient requirements of modern real-time applications. Reconfigurable hardware platforms such as Field-Programmable Gate Arrays (FPGAs) provide a powerful alternative by enabling architectural customization, intrinsic parallelism, and optimized hardware acceleration. …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 3, Issue 2, 2025 · pp. 11–22 Read article
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Building Knowledge with a Hands-on 8-bit CPU Architecture Simulation Kit for Students
Abstract: It is now crucial for students studying electronics and information technology to comprehend computer architecture and logic design. Hands-on, practical instruction is required to assist students in understanding Computer Organization and Architecture (COA). Our kit, which covers essential components including bus interfaces, arithmetic, and logic units (ALU), memory structures, and functional registers, is based on the Von Neumann architecture. Theoretical techniques like block diagrams and top level diagrams are typically …
Published in Journal of Electronic Design Technology · Vol. 15, Issue 3, 2024 · pp. 1–9 Read article