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153 articles for “CMOS design”
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A Comparative Analysis of Various Flipped Voltage Follower Cells
Abstract: Flipped voltage follower (FVF) cell is used for designing low-voltage/low-power analog circuits. It can operate with a single supply voltage, less than the sum of the threshold voltages of a PMOS and NMOS transistor. The three different configurations of the FVF cell namely conventional FVF, FVF using level shifter (FVFLS) and FVF using bulk driven technique (FVFBD) are presented. Various parameters such as input/output swing, gain, bandwidth and power dissipation …
Published in Journal of Microelectronics and Solid State Devices · Vol. 4, Issue 2, 2017 · pp. 1–8 Read article
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Characterization of High Performance Third Generation Current Conveyor using CMOS Technology
Abstract: In this paper, Conventional Third generation(CCIII) and Dual-Output Cascoded Third Generation Current Conveyor(DOCCIII) is presented. Here, both are simulated in ELDO SPICE Mentor Graphics using 90 nm CMOS technology at 0.8 V supply voltage. High performance cascoded current mirrors provide high output impedance. Third generation current conveyer has the advantages of wide current and voltage bandwidths, controlled intrinsic resistances at terminals X,Y and Z. By the use of high performance …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 2, 2015 · pp. 54–63 Read article
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A Nobel Approach of Designing A 4 Bit Carry Skip Adder Using Reversible Logic
Abstract: This paper presents a method to designing Various Adder Circuits using CMOS Logic Style for Energy-Efficient Arithmetic Applications. We present Ripple Carry Adder, Carry Bypass Adder, Carry Look Ahead Adder and Carry Skip Adder in CMOS logic styles that lead to have reduced power-delay product (PDP). We executes a comparison against each other adders which finally provide result as having a low PDP, with reference to power consumption, speed and …
Published in Journal of VLSI Design Tools and Technology · Vol. 11, Issue 2, 2021 · pp. 24–34 Read article
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Performance Analysis of Bootstrapping Techniques to Overcome the Threshold Voltage Drop in NMOS Logic Design
Abstract: Abstract: In this paper, we study the concept of bootstrapping techniques and analyzed its performance in digital CMOS circuits. These bootstrapping circuits are used to increase the gate voltage of transistors so that drain node voltage can be pulled high to overcome the threshold voltage drop problem in NMOS logic design. Also discuss the drawback associated with voltage bootstrapping techniques in NMOS logic design that is sneak path problem between …
Published in Journal of Semiconductor Devices and Circuits · Vol. 6, Issue 1, 2019 · pp. 15–20 Read article
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Design and Performance Analysis of Full Adder Cell using FinFET Technique at 32nm Technology
Abstract: AbstractIn this paper, discussed is the comparative analysis of complementary MOS (CMOS) and dual gate-FinFET (fin shaped field effect transistor) based full adder cell design. To reduce the average power, average current and maximum current of 1-bit full adder circuit a new high DG-FinFET technique is presented. Use of double-gate FinFET technology provides low leakage and high performance operation. For MOSFET transistor model, a predictive technology model (PTM) BSIM4 and …
Published in Journal of Microelectronics and Solid State Devices · Vol. 4, Issue 3, 2017 · pp. 1–8 Read article
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Ultra Low-Power 9-Transistor Flip-Flop Design
Abstract: AbstractThe use of very large scale integration technology in high performance computing, wireless communication, consumer electronics has been rising at a very fast rate. The challenge for VLSI technology is mainly in leakage power consumption. Flip-Flops (FFs) are the basic storage elements used extensively in digital system designs. It accounts for 20%–45% of the total system power and may considerably impact the chip area. In this paper, an ultra-low-power true …
Published in Journal of Microelectronics and Solid State Devices · Vol. 5, Issue 3, 2018 · pp. 27–32 Read article
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Performance Comparison of Noise-Tolerant, High- Performance CMOS Domino Logic Configurations
Abstract: In high-performance VLSI chip design, domino logic configuration is often preferred over static logic due to its faster operation and smaller area footprint, especially in deep submicron (DSM) technology. However, DSM noise has become a significant challenge in domino-based circuits, leading to compromises in the reliability and signal integrity of integrated circuits (ICs). The switching threshold of domino logic, defined as the input voltage level at which the gate output …
Published in Journal of Semiconductor Devices and Circuits · Vol. 12, Issue 2, 2025 · pp. 35–50 Read article
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Study and Analysis on Multi-gate MOSFET Design
Abstract: AbstractMulti-gate MOSFET is the emerging technology that is used in the area of low-power VLSI design. Multi-gate devices provide much better advantages over conventional MOSFET. As less power dissipation, decrease size, and more operational value could be obtained. Multi-gate MOSFET devices also reduce cost of production. Thus, design of electronics devices based on multi-gate technology is beneficial in today’s requirement. Basic MOSFET due to its reduction in size shows short …
Published in Journal of Semiconductor Devices and Circuits · Vol. 7, Issue 1, 2020 · pp. 1–7 Read article
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Power-Efficient Design Strategies for Static Random Access Memory with Memory Blocks: A Review
Abstract: For many years, CMOS technology has been able to achieve high integration density and great performance by scaling down its feature size and threshold voltage. Power consumption has been a major concern in VLSI design due to the ongoing drop in aspect ratio and the related improvements in chip density and operation frequency. SRAM is a type of random-access memory in which an interruption in power causes data loss. For …
Published in Journal of Microcontroller Engineering and Applications · Vol. 10, Issue 3, 2023 · pp. 23–32 Read article
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Implementation and Analysis of Full Adder using low Power Adiabatic Techniques
Abstract: AbstractIn this study, authors have discussed, designed and compared the low power adiabatic logic energy efficient recovery logic (ECRL) and positive feedback of adiabatic logic (PFAL) with conventional Complementary Mosfet (CMOS) logic. A one-bit full adder using these design techniques are implemented and results are compared like power, delay, transistor count and power delay product. Tanner tool v13 is used for designing of schematic and simulation. From the result, it …
Published in Journal of Semiconductor Devices and Circuits · Vol. 5, Issue 2, 2018 · pp. 1–8 Read article
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System Level Modeling of ISMB Quadrature Transceiver
Abstract: In this paper, a new ISMB quadrature transceiver system-level design architecture is presented along with its referenced mathematical models and these were verified using state-of-the-art system modeling tools. Unlike a K-TEK’s receiver, it does not suffer from the timing and template matching problems, and it circumvents processing at high frequencies, thereby reducing the on-chip circuit complexity and power consumption. Hilbert transform has been used at the output of the demodulator …
Published in Journal of VLSI Design Tools and Technology · Vol. 2, Issue 1-2-3, 2012 · pp. 108–117 Read article
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A well-planned strategy for a career path in VLSI design
Abstract: Very Large Scale Integration (VLSI) design is still one of the most active and important areas of the semiconductor industry. It is behind new developments in AI, 5G, automotive electronics, and high-performance computing. As companies like Intel, TSMC, and NVIDIA work to improve advanced-node technology, the need for qualified VLSI engineers is growing. However, people who want to work in this industry typically don't know what technical skills, tools, and …
Published in Journal of VLSI Design Tools and Technology · Vol. 16, Issue 1, 2026 · pp. 28–39 Read article
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A Circuit Approach for CMOS VLSI Circuit Leakage Power Reduction
Abstract: Despite the fact that scaling CMOS technology boosted speed, leakage currents always remained an issue. The issue has gotten worse as the scaling has gone into the UDSM (ultra-deep-submicron) range. In order for the circuit to function effectively, these unwanted leakage currents must be reduced to a minimum. It is challenging to create these leakage-free nano-scale CMOS circuits. In this work, the issue of leakage power is addressed, which occurs …
Published in Research & Reviews: A Journal of Embedded System & Applications · Vol. 10, Issue 3, 2022 · pp. 7–18 Read article
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Improvement of Design Issues in FinFET based Design Techniques for XOR and XNOR Circuits at 45 nm Technology
Abstract: The scaling of conventional CMOS circuit inclines to the short channel effect due to leakage current increase in the circuit. To minimize the short channel effect, FINFET can be used in place of conventional CMOS circuits. This paper demonstrates comparative performance study of high speed, low power and low voltage on XOR and XNOR digital circuit. This paper assesses and compares the performance of XOR and XNOR logic circuits. This …
Published in Journal of Electronic Design Technology · Vol. 5, Issue 1, 2014 · pp. 22–35 Read article
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Low-Offset High Speed CMOS Voltage Comparator using 180 nm Technology
Abstract: A low Off-Set high-speed two-stage dynamic comparator is presented. In this circuit, PMOS transistors are used at the input of the first and second stages of the comparator. At the evaluation phase, the second stage is activated after the first stage with a predetermined delay to achieve a controllable pre-amplifier gain. Also, the first stage is turned off after the delay to reduce overall power consumption. Simulation results in 0.18µm …
Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 3, 2017 · pp. 21–27 Read article
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Design and Analysis of an Efficient Fast Low Power 1 Kb SRAM Cell Using 90nm and 45 nm Microwind Technology
Abstract: This paper proposes a review on study and analysis of an efficient fast low power 1 Kb SRAM cell using 90 and 45 nm Microwind technology. In this paper we have proposed the tentative improvement in performance parameters of SRAM cell like power dissipation, read or write speed, stability and signal to noise margin ration (SNM) using CMOS scaling.Keywords: SRAM, CMOS scaling, MicrowindCite this ArticlePathrikar A.K, Deshpande Rajkumar S. Design …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 2, 2015 · pp. 1–3 Read article
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Decimator Design for Sigma-Delta ADC
Abstract: This paper describes the design of a decimator which is used in digital signal processing as well as 10-bit sigma-delta analog-to-digital converter to down sample the incoming signal for further applications. It is also used for verification of the sigma-delta modulator functionality to reconstruct the incoming signal. The design has been carried out using 180 nm TSMC, CMOS foundry parameters for spice level 49 model parameters in TANNER EDA (Tspice). …
Published in Journal of VLSI Design Tools and Technology · Vol. 2, Issue 1-2-3, 2012 · pp. 16–28 Read article
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Evaluation of OTA Amplifier Using EEG Signals
Abstract: AbstractOver the last few years, there has been a tremendous exploration in VLSI industries in response to scaling trends towards deep submicron technology. Demand for low power and efficient amplification are rising in day-to-day life. In the process of scaling the CMOS nanometer demand low supply, which is helped to design digital circuit realization at very low power consumption. But it is not valid for analog circuit realization. The related …
Published in Trends in Opto-electro & Optical Communication · Vol. 10, Issue 2, 2020 · pp. 5–14 Read article
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Low Power and High Speed Techniques for Sequential Circuits
Abstract: This paper proposes techniques like MT-CMOS, power gating, dual stack, Galeor and Lector to reduce the leakage power. A D-Flip Flop has been designed using these techniques and power dissipation is calculated and is compared with general CMOS logic of D Flip Flop. Simulation results show the validity of the proposed techniques is effective to save power dissipation and to increase the speed of operation of the circuits to a …
Published in Journal of Power Electronics and Power Systems · Vol. 4, Issue 3, 2014 · pp. 41–45 Read article
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QCA-based Implementation of Budget-friendly and Energy-Efficient Exclusive-OR/Exclusive-NOR Gates
Abstract: Quantum-dot cellular automata (QCA) is a novel nanoscale computational approach that proposes reduced dimensions, lower power consumption, increased speed, and deliberate design as a solution to the scaling challenge associated with CMOS technique. QCA is a nascent nanotechnology that utilizes the Coulomb repulsion principle. Quantum computing has emerged as a highly effective paradigm for the creation of energy-efficient hardware at the nanoscale. This article presents implementation of a very efficient …
Published in International Journal of Electro-Mechanics and Material Behaviour · Vol. 1, Issue 2, 2023 · pp. 1–6 Read article