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19 articles for “digital signal processors”
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High Throughput RISC Processor Design Using Vedic Mathematics: A Review
Abstract: The load on general processor is increasing. It is of the utmost importance in the arithmetic unit for fast operations. Multipliers have a significant impact on how well the Arithmetic Unit performs. In this way, analysts are constantly looking for new methodologies and equipment to execute number juggling activity in tremendous proficient manner in the terms of speed and region. Vedic Science is the old arrangement of math which has …
Published in Research & Reviews: A Journal of Embedded System & Applications · Vol. 10, Issue 2, 2022 · pp. 29–33 Read article
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A Novel Architecture of Control System Processor Using Field Programmable Gate Array
Abstract: This paper presents a reconfigurable architecture of control system processor. The performance of the proposed architecture has been evaluated by taking different controllers and phase lead and phase lag networks. We designed the architecture of the processor and realizing the architecture using adder, multiplier, delay unit and validate it in the FPGA, which show that the hardware scheme is feasible for practical application. The experimental results clearly reveal the novelty …
Published in Journal of Microcontroller Engineering and Applications · Vol. 2, Issue 2, 2015 · pp. 13–20 Read article
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A Visible Light-based Indoor Navigation and Localization Solution for Visually Criticized Users
Abstract: Visible Light Communication is seen as a promising option for 5G communication because to its characteristics such as operating in a non-licensed frequency spectrum, offering high bandwidth, using minimal power, and being immune to electromagnetic interference. This property allows light waves to transmit data faster and convey more information, making VLC a promising solution for providing universal electronic navigation assistance to visually challenged individuals. VLC utilizes the visible light spectrum …
Published in Journal of Telecommunication, Switching Systems and Networks · Vol. 10, Issue 2, 2023 · pp. 22–34 Read article
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Performance Analysis of 1-Bit Half Adder using Different Combinational MOS Logics
Abstract: AbstractAdder is required for many processors designing like microprocessors, digital signal processors, image processing and various VLSI applications. The overall performance of system depends upon the adder circuits due to its presence mainly in critical paths of system. This paper presents half adder circuits using different combinational MOS logics. All the circuits were analyzed to find the most suitable circuit which consumes less power without costing the speed of the …
Published in Journal of Microelectronics and Solid State Devices · Vol. 4, Issue 3, 2017 · pp. 19–27 Read article
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Area and Speed Efficient Floating Arithmetic Logic Unit Implementation on Hybrid FPGAS
Abstract: Proposed design of an Area and Speed optimized field arithmetic logic unit (FALU) for modern computing of advanced processors, as we are aware that in most of the DSP (Digital Signal Processors) FALU is a critical component for continuous calculation of signs and ongoing information to meet the constant situation of sign handling it is exceptionally needed to make calculation quicker as could be expected so we have thought of …
Published in Research & Reviews: A Journal of Embedded System & Applications · Vol. 9, Issue 3, 2021 · pp. 29–34 Read article
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Low-Power Reconfigurable Digital Filter Design Using FPGA for IoT Edge Devices
Abstract: The rapid evolution of the Internet of Things (IoT) has led to an exponential increase in the deployment of edge devices that continuously process real-time sensor data under strict power, latency, and computational constraints. Digital filtering remains a critical operation in these devices, supporting tasks such as noise removal, data conditioning, and feature extraction for intelligent decision-making. However, conventional filter implementations on microcontrollers or fixed digital signal processors often struggle …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 3, Issue 2, 2025 · pp. 23–34 Read article
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A Novel Design for High Speed & Area Efficient Compressor Based Vedic Multiplier
Abstract: Multipliers are the most important part in any arithmetic and logic unit, AbstractMultipliers are the most important part in any arithmetic and logic unit, accumulators and digital signal processors. Due to the increasing constraints on delay, the design of faster multipliers is emphasized. Among several multipliers, Vedic multipliers are preferred for their speed of operation. Here the proposed Vedic multiplication techniques are based on “URDHVA TIRYAKBHYAM” a fast and efficient …
Published in Journal of Microelectronics and Solid State Devices · Vol. 5, Issue 3, 2018 · pp. 1–10 Read article
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Performance Comparison of Noise-Tolerant, High- Performance CMOS Domino Logic Configurations
Abstract: In high-performance VLSI chip design, domino logic configuration is often preferred over static logic due to its faster operation and smaller area footprint, especially in deep submicron (DSM) technology. However, DSM noise has become a significant challenge in domino-based circuits, leading to compromises in the reliability and signal integrity of integrated circuits (ICs). The switching threshold of domino logic, defined as the input voltage level at which the gate output …
Published in Journal of Semiconductor Devices and Circuits · Vol. 12, Issue 2, 2025 · pp. 35–50 Read article
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Implementation of an Adaptive Filter Algorithm with Subband Filtering Approach on Acoustic Echo Cancellation
Abstract: This paper focuses on model and its realization on digital signal processors (DSP) for suppressing annoying acoustic echoes in telephone and mobile communication applications. For cost sensitive subscriber devices and high quality voice communications the aims are 1) minimum computational complexity 2) maximum convergence speed and 3) maximum echo attenuation. The chosen method for the echo cancellation involves a sub band decomposition performing the adaptive filtering in subbands at a …
Published in Current Trends in Signal Processing · Vol. 4, Issue 3, 2014 · pp. 28–34 Read article
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Implementation of 16-Bit Qam Using Texas Instruments
Abstract: In this paper, an implementation of 16-bit QAM is performed where there is a high use of Digital Video Broadcasting Cable (DVB-C), as there is increase in the usage the bandwidth requirement for each user is mutually increasing. Due to this, there is spectral congestion caused and drastic improvements have been taken in the field of communications. QAM multilevel modulation can offer an attractive solution to current bandwidth restriction in …
Published in Journal of Microelectronics and Solid State Devices · Vol. 2, Issue 2, 2015 · pp. 14–20 Read article
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An Area Delay Optimized Carry-Select Adder
Abstract: In arithmetic and logic unit of digital signal processor (DSP), adder is the important hardware unit. Carry select adder (CSLA) is the best example of the adder used in DSP and it is widely used in many data processors to increase speed. So, the adder performance affects the overall system-performance. The Regular Square root (SQRT) CSLA consists of two Ripple Carry Adders (RCA), so it consumes more area due to …
Published in Journal of VLSI Design Tools and Technology · Vol. 8, Issue 3, 2018 · pp. 10–14 Read article
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Area Efficient Layout Design of Two Bit Magnitude Comparator Using Novel Strategy
Abstract: The development of digital circuits, digital signal processors and other data processing integrated circuits, comparators are challenged by large area consumption. Comparator is most basic and fundamental component that performs comparison operation. This paper proposes a new approach to design an area efficient two bit magnitude comparator. Comparison is done on the grounds of area and power consumed between circuit designed by novel strategy and preexisting CMOS technique. The novel …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 3, 2016 · pp. 1–6 Read article
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Reducing Crosstalk in Arithmetic and Logic Unit Part of a Processor
Abstract: Crosstalk is common in any digital systems and may occur due to coupling of signals which eventually have an impact on the working of a system. In this paper, an attempt is made to study the effect of crosstalk in 8-bit slice ALU, designed using 120 nm technology and suggested a method to reduce the crosstalk.Keywords: ALU, signal integrity, metal layers
Published in Journal of VLSI Design Tools and Technology · Vol. 3, Issue 1, 2013 · pp. 28–32 Read article
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Comparative Analysis of Partial Product Addition in Vedic Urdhva Tiryakbhyam Multiplier
Abstract: Multiplication is one of important operations performed in many digital signal processing applications. Hence the performance of the multiplier will affect the overall performance of the DSP processor. The methods like booth multiplier, and array multiplier are used. Vedic multiplication technique had proved its importance in getting the speed of multiplication. It is required to add the generated partial products quickly, to generate the result of multiplication faster. To add …
Published in Journal of VLSI Design Tools and Technology · Vol. 13, Issue 1, 2023 · pp. 15–32 Read article
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Implementation of Audio Streaming System Using Bluetooth Standards
Abstract: Bluetooth is one of the most famous short range wireless communication standards. Almost all modern electronic gadgets available in the market are equipped with Bluetooth support. Analog television or the I-pod or simple radio systems are the devices which are yet not equipped with such facilities. The paper discusses the embedded hardware which enables any analog or digital devices, which are capable of generating analog or digital signals, to send …
Published in Journal of Electronic Design Technology · Vol. 5, Issue 3, 2014 · pp. 22–30 Read article
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Design and Development of a Multifunction FPGA-based Data Acquisition System using Nonlinear Duty-cycle Modulation Technique
Abstract: AbstractA new generation of DAQ based on duty-cycle modulation technique is presented. It describes the design and prototyping of a FPGA-based data acquisition and signal generation board using the duty-cycle modulation technique and with computer-based software interface. The system is built around the DE0-Nano development board that embeds an Altera cyclone IV FPGA in which a NIOS II processor running at 100 MHz has been instantiated. The conversion technique from …
Published in Journal of Electronic Design Technology · Vol. 10, Issue 3, 2019 · pp. 8–26 Read article
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Graphene–Perovskite Hybrid Opto-Electronic Modulators for Ultra-Low Power Optical Communication
Abstract: This paper proposes a novel self-adaptive neuromorphic opto-electronic transceiver architecture designed to enhance the intelligence, adaptability, and efficiency of next-generation optical communication networks. The proposed system integrates neuromorphic computing principles with photonic signal processing to enable real-time learning, dynamic resource allocation, and autonomous compensation of channel impairments such as dispersion, nonlinearities, and noise. Unlike conventional transceivers, the developed model employs spiking neural networks embedded within opto-electronic circuits to mimic biological …
Published in Trends in Opto-electro & Optical Communication · Vol. 16, Issue 1, 2026 · pp. 41–52 Read article
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Design and Implementation of a 4-Bit Breadboard CPU Using Digital Integrated Circuits
Abstract: This paper presents the design and hardware realization of a simple 4-bit CPU built using discrete TTL integrated circuits on a breadboard. The CPU employs a 4-bit common data bus with tri-state buffers for device arbitration, three 4-bit registers (Register A, Register B, and an Output Register) implemented with 74LS175 quad D flip-flops, and a 4-bit ALU for addition/subtraction using a 74LS83 adder and XOR gates. Manual control signals (load, …
Published in Journal of Electronic Design Technology · Vol. 17, Issue 2, 2026 · pp. 30–42 Read article
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Design and Implementation of 256-bit Vedic Multiplier on Reconfigurable Platform
Abstract: Multiplication is a fundamental arithmetic operation in digital signal processing and embedded systems. Traditional multiplier architectures often suffer from increased latency and resource utilization when scaled to higher bit widths. Vedic Mathematics, an ancient Indian technique, offers a novel and efficient alternative. This paper presents the design and implementation of a 256-bit Vedic multiplier using the Urdhva Tiryakbhyam Sutra on a reconfigurable hardware platform, specifically FPGA. The proposed architecture decomposes …
Published in Journal of Materials & Metallurgical Engineering · Vol. 15, Issue 3, 2025 · pp. 56–65 Read article