Comparative Analysis of Partial Product Addition in Vedic Urdhva Tiryakbhyam Multiplier

M S; B. S. Agarkar

Abstract

Multiplication is one of important operations performed in many digital signal processing applications. Hence the performance of the multiplier will affect the overall performance of the DSP processor. The methods like booth multiplier, and array multiplier are used. Vedic multiplication technique had proved its importance in getting the speed of multiplication. It is required to add the generated partial products quickly, to generate the result of multiplication faster. To add the generated partial products, different schemes are used such as ripple carry adders, carry look-ahead adders, carry save adders etc. This paper study aims to use the Urdhva Tiryakbhyam method of Vedic multiplication and present the comparison of different partial product addition methods. The comparison shows that the proposed method with half adders and full adders is better alternative if little increase in propagation delay is accepted at the cost of reduced area i.e., slices and LUTs; the proposed method of half adders and full adders is better choice for addition of partial products. Also, the power dissipation of this method is less as compared to other methods

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