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23 articles for “XOR”
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Design and Simulation of Full Adder-Based CMOS 4-2 Compressor using CMOS XOR-XNOR Logic
Abstract: This study utilizes the recent development of CMOS transistors to construct an energy-efficient Full adder-based CMOS 4-2 compressor. The CMOS Exclusive-OR-Exclusive-NOR component and multiplexer used in the transmission logic of the novel CMOS compressor include eight transistors. The XOR-XNOR logic style is the most efficient and effective due to its speed and reduced power consumption. Utilizing an operational supply voltage of 0.7 V and 90nm CMOS technology, the Cadence Virtuoso …
Published in Recent Trends in Electronics Communication Systems · Vol. 12, Issue 3, 2025 · pp. 1–8 Read article
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Improvement of Design Issues in FinFET based Design Techniques for XOR and XNOR Circuits at 45 nm Technology
Abstract: The scaling of conventional CMOS circuit inclines to the short channel effect due to leakage current increase in the circuit. To minimize the short channel effect, FINFET can be used in place of conventional CMOS circuits. This paper demonstrates comparative performance study of high speed, low power and low voltage on XOR and XNOR digital circuit. This paper assesses and compares the performance of XOR and XNOR logic circuits. This …
Published in Journal of Electronic Design Technology · Vol. 5, Issue 1, 2014 · pp. 22–35 Read article
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Photonic Design of Two Input XOR Gate at 50 Gbps Data Rate
Abstract: This manuscript explores the photonic design of two input XOR gate at 50 Gbps data rate. In the photonic circuit, each component exercised supports for the light wave propagation. The performance of optical XOR gate is alike to their digital variant. The key constituents utilized in designing of this photonic network are 2×2 optical coupler and semiconductor optical amplifier. The proposed design is executed by the igniting the nonlinear attributes …
Published in Journal of Microelectronics and Solid State Devices · Vol. 4, Issue 2, 2017 · pp. 32–39 Read article
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Review Paper To Design a Low Power CNTFET Based XOR Gate
Abstract: The continuous scaling down of Silicon technology leads to various critical challenges and reliability issues such as short channel effect, high leakage current, interconnect problems, etc. CNTFET is the most probable substitutes to traditional MOSFET. The CNTFET device based circuits portray advantages with its better control over the device channel, reduced leakage current, reduced short channel effects. The CNTFET based XOR gate circuits incur the minimum power and energy dissipation. …
Published in Journal of VLSI Design Tools and Technology · Vol. 8, Issue 1, 2018 · pp. 48–53 Read article
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Implementation of Optical XOR Gate and Gray to Binary Code Converter Using Mach-Zehnder Interferometer
Abstract: AbstractWith the progress in optical communication system, optical networks are demanding of all optical devices to improve the speed, power and to reduce the attenuation during transmission of signals. In this paper, execution of gray to binary code converter with the aid of semiconductor optical amplifier (SOA) based Mach-Zehnder interferometer (MZI) is proposed, with the help of all-optical XOR logic gate, which is also demonstrated by using SOA-MZI, where CW …
Published in Trends in Opto-electro & Optical Communication · Vol. 7, Issue 1, 2017 · pp. 1–5 Read article
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A New Robust and High-Performance Sub-threshold XOR/XNOR Circuit
Abstract: This paper proposes an efficient 5-Transistor XOR/XNOR circuit. The proposed circuit exhibits higher performance, lower power dissipation and power-delay product (PDP). The proposed design is compared with existing XOR/XNOR circuits for sub-threshold operation. It offers 1.31 × improvement in delay and 1.28 × improvement in PDP compared to its counterpart. It proves its robustness by offering 2.27 × improvement in delay variability, 1.32 × improvement in power dissipation variability and …
Published in Journal of Semiconductor Devices and Circuits · Vol. 1, Issue 1, 2014 · pp. 37–46 Read article
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Reconfigurable AES Based AEAD For Multi-Mode Operation with Lightweight Compatibility
Abstract: The proposal is for a lightweight, multi-mode, reconfigurable authenticated encryption system with associated data (AEADs) based on AES. It is challenging to effectively integrate different AEADs in hardware because each one has its own mode of operation and/or subfunctions, even though some major AEADs share several basic components (such as the XOR-Encryption-XOR (XEX) scheme, block chaining, and advanced encryption standard (AES). This paper proposes hardware that effectively combines the basic …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 3, Issue 1, 2025 · pp. 54–68 Read article
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Using a Lightweight Cryptographic Algorithm to Improve Cloud Computing Data Security
Abstract: The use of cloud computing technology allows for the storage of vast amounts of data. It is now crucial to protect the integrity, confidentiality, privacy, and handling processes of cloud computing data from attackers. To improve data security in cloud computing, a novel, lightweight cryptographic algorithm was put forth in this study. The algorithm, which is a 16-byte or 128-bit block cipher, requires a 16-byte or 128-bit key to encrypt …
Published in Recent Trends in Parallel Computing · Vol. 10, Issue 1, 2023 · pp. 22–34 Read article
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Design and Simulation of Low-power, High-speed Effective Area Mux Based One-bit Full Adder Using CMOS Technology
Abstract: Our findings reveal a novel kind of circuit capable of performing both XOR and XNOR operations in parallel. Power dissipation and delay are both greatly reduced in the proposed circuits due to their low output capacitance as well as minimal short-circuit power dissipation. We show six new hybrid 1-bit full-adder (FA) circuits that take use of the XOR-XNOR or XOR/XNOR gates' special full-swing function. Each potential circuit layout has both …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 1, Issue 1, 2023 · pp. 25–33 Read article
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QCA-based Implementation of Budget-friendly and Energy-Efficient Exclusive-OR/Exclusive-NOR Gates
Abstract: Quantum-dot cellular automata (QCA) is a novel nanoscale computational approach that proposes reduced dimensions, lower power consumption, increased speed, and deliberate design as a solution to the scaling challenge associated with CMOS technique. QCA is a nascent nanotechnology that utilizes the Coulomb repulsion principle. Quantum computing has emerged as a highly effective paradigm for the creation of energy-efficient hardware at the nanoscale. This article presents implementation of a very efficient …
Published in International Journal of Electro-Mechanics and Material Behaviour · Vol. 1, Issue 2, 2023 · pp. 1–6 Read article
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An Efficient Counter Using Modified Upper and Lower SVL Techniques and TSPCL
Abstract: Low power VLSI has emerged as the fundamental building block of the modern electronic era. This leads to a substantial paradigm shift where both power dissipation, performance and area of utmost importance. In the earlier time of fabrication, power dissipation was mainly neglected due to low device density and low operating frequency needed for computation. But in modern technological era, the need for high device density, higher operating frequency, proliferation …
Published in Research & Reviews : Journal of Physics · Vol. 13, Issue 2, 2024 · pp. 37–43 Read article
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Spintronic Logic Circuits for Ultrafast Processing
Abstract: Spintronic logic has emerged as one of the most promising post-CMOS paradigms capable of addressing the speed, density, and energy challenges of deeply scaled silicon technologies. By relying on the intrinsic properties of electron spin and magnetization dynamics, spintronic devices—particularly Magnetic Tunnel Junctions (MTJs), Spin-Transfer Torque (STT), and Spin–Orbit Torque (SOT) structures—enable ultrafast, non-volatile data processing with significantly reduced energy consumption. Despite remarkable device-level advancements, circuit- level realization of high-speed, …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 3, Issue 2, 2025 · pp. 35–43 Read article
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64 Bit ALU DESIGN USING VEDIC MATHEMATHICS
Abstract: High-speed arithmetic operations are crucial for better performance in contemporary digital systems. Particularly for high bit-width operations, conventional arithmetic logic units (ALUs) frequently experience increased latency and complexity. This work presents the design and implementation of a 64-bit Arithmetic Logic Unit (ALU) using notions from Vedic mathematics. The suggested design makes use of a Kogge-Stone Adder for effective addition and the Urdhva Tiryagbhyam sutra for quick multiplication. Among other mathematical …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 4, Issue 1, 2026 Read article
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Design and Implementation of a 4-Bit Breadboard CPU Using Digital Integrated Circuits
Abstract: This paper presents the design and hardware realization of a simple 4-bit CPU built using discrete TTL integrated circuits on a breadboard. The CPU employs a 4-bit common data bus with tri-state buffers for device arbitration, three 4-bit registers (Register A, Register B, and an Output Register) implemented with 74LS175 quad D flip-flops, and a 4-bit ALU for addition/subtraction using a 74LS83 adder and XOR gates. Manual control signals (load, …
Published in Journal of Electronic Design Technology · Vol. 17, Issue 2, 2026 · pp. 30–42 Read article
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Which is the Best 10T Static CMOS Full Adder for Ultralow-Power Applications?
Abstract: This paper presents the analysis of various 10-transistor CMOS 1-bit full adder circuits in terms of their output levels and finds out the suitable adder cell at 200 mV in subthreshold region at 16-nm technology node for ultra-low power applications. This paper also provides worst case output levels (sum and carry) of all the analyzed adder cells (which are presented in the paper) for various input combinations.Keywords: CMOS, carry, 2:1 …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 1, 2015 · pp. 45–50 Read article
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Design of FPGA Based ALU Using Reversible Logic Gates
Abstract: Reversible or information misfortune less circuits has applications in computerized signal handling, correspondence, PC design and nanotechnology. Reversible technique is utilized to minimize heat that happens in traditional circuits by keeping the loss of data. This paper proposes a reversible configuration of an ALU. This ALU comprises of eight operations, five are of arithmetic category and three are from logical category operations. An arithmetic operations incorporate add, sub, increase by …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 3, 2016 · pp. 15–21 Read article
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Design and Simulation of 4-bit Multiplier using Carry Look-Ahead Adder at Transistor Level
Abstract: Multiplication is a basic operation performed in the Arithmetic Logic Unit, Digital signal processing, Floating-point unit and Application specific integrated circuits. This paper deals with the design and simulation of the 4-bit multiplier using a carry look-ahead adder at the transistor level. The total design process involves hierarchical implementation. Where the basic gate operations like AND, OR, NOT, and XOR are repeatedly used for designing the entire circuit. So, the …
Published in Journal of VLSI Design Tools and Technology · Vol. 11, Issue 3, 2021 · pp. 10–18 Read article
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Performance Study for Optical Half Subtractor Based on SOA
Abstract: AbstractThis article explores for an optical binary half subtractor design which is based on the semiconductor optical amplifiers nonlinear characteristics. For that, the difference output operation of data’s has been realized in the one branch with semiconductor optical amplifier realizing XOR operation and for borrow operation the AND logic operation of the data B with complaint of data A is realized in the other semiconductor optical amplifier branch. Accordingly the …
Published in Trends in Opto-electro & Optical Communication · Vol. 5, Issue 3, 2015 · pp. 50–57 Read article
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Implementation of All-Optical Logic Gate using SOA-MZI Structures
Abstract: AbstractSemiconductor optical amplifiers (SOAs) are very attractive nonlinear elements for the realization of different logic functions, since they can exhibit a strong change of the refractive index together with high gain. In this paper, a principle of operation, simulation step and experimental result of different all-optical logic gate (AND Gate, OR Gate, XOR Gate) are well presented. These gates are based on the nonlinearities on SOAs. The experimental results are …
Published in Trends in Opto-electro & Optical Communication · Vol. 3, Issue 3, 2013 · pp. 13–21 Read article
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Improved Performance by Using k-means Clustering in Vehicular Ad Hoc Network
Abstract: AbstractVANETs are formed by applying the principles of MANETs, in which all node, i.e., vehicles can pursue traffic law with high speed. VANETs support two types of communication: vehicle - to- vehicle (V2V) and vehicle to-infrastructure (V2I). Vehicles communicate to RSU for the exchange of keys for the security purpose and RSU communicate to Authentication Server (AS) for the formation of secret keys. But in existing work they perform nonsymmetric …
Published in Journal of Communication Engineering & Systems · Vol. 7, Issue 1, 2017 · pp. 17–24 Read article