Search
153 articles for “CMOS design”
-
Design and Analysis of Energy-Efficient GDI Cell and Its Impact on Multipliers
Abstract: VLSI design technology suffers from three major issues such as area, speed and power. Among these issues, power is a serious concern that is yet to be considered. So, in this paper, power is concerned more as compared to area and speed. GDI (gate diffusion input) is one of the common techniques used in VLSI design systems to reduce power consumption. Due to its high performance and less area overhead, …
Published in Journal of VLSI Design Tools and Technology · Vol. 4, Issue 2, 2014 · pp. 32–36 Read article
-
Comparative Analysis of CMOS CNFET and Memristor Based Full Adder Circuits and CMOS Memristor Based Multiplexer Circuits
Abstract: Continued developments in microelectronics technology have led to a myriad of new compute- intensive applications at the micro-edge, such as artificial intelligence and signal and image processing. Multiplication is a crucial arithmetic process in such applications. However, large logic complexities typically seen in traditional multipliers generate combinatorial blocks with long chains of cascaded carry addition. As such, energy efficiency has remained a primary design challenge for these applications, when powered …
Published in Journal of VLSI Design Tools and Technology Read article
-
Comparative Analysis of CMOS CNFET and Memristor Based Full Adder Circuits and CMOS Memristor Based Multiplexer Circuits
Abstract: Continued developments in microelectronics technology have led to a myriad of new compute-intensive applications at the micro-edge, such as artificial intelligence and signal and image processing. Multiplication is a crucial arithmetic process in such applications. However, large logic complexities typically seen in traditional multipliers generate combinatorial blocks with long chains of cascaded carry addition. As such, energy efficiency has remained a primary design challenge for these applications, when powered by …
Published in Journal of VLSI Design Tools and Technology · Vol. 12, Issue 2, 2022 · pp. 22–33 Read article
-
Suitability of Various Low Power Strategies for SRAM Design: A Survey
Abstract: In very high performance system on chip, static power dissipation plays a dominant role compared to dynamic component and it increases with technology scaling. Scaling of bulk MOSFET faces more and more challenges at 45 nm technology or below by producing short channel effect (SCE) which leads to increase in leakage current. An obstacle with bulk MOSFET at 45 nm or below gate length includes SCE, subthreshold leakage and gate …
Published in Journal of Semiconductor Devices and Circuits · Vol. 2, Issue 1, 2015 · pp. 6–13 Read article
-
Development of Polymer Based SRAM Cell with Enhance Low Power Performance
Abstract: Low-power memory technologies are in high demand with the rapid growth of portable electronics and energy-efficient computing systems. Static random-access memory (SRAM) plays a crucial role in processors, cache memories, and system-on-chip applications due to their speed and reliability. Static Random Access Memory (SRAM) is typically implemented using complementary MOS (CMOS) technology, which integrates both PMOS (P-channel Metal–Oxide–Semiconductor) and NMOS (N-channel Metal–Oxide–Semiconductor) transistors. However, as technology scales to deep submicron …
Published in Journal of Polymer & Composites · Vol. 14, Issue 1, 2026 · pp. 1439–1448 Read article
-
Time Domain Analysis in an On-chip High Speed RLCG Interconnection Network at 0.18 µm Technology
Abstract: In this model, the time domain waveform is evaluated for calculation of delay time, peak time, settling time, damping ratio and natural frequency for a second order RLCG interconnect network. It can also be used for multiple interconnect systems but for higher order systems it is ignored due to accurate analysis. The model is applied to a single resistance-inductance-capacitance-conductance model which can also be extended to multi-interconnect systems to analyze …
Published in Journal of VLSI Design Tools and Technology · Vol. 1, Issue 1-2-3, 2011 · pp. 57–67 Read article
-
True Random Number Generators Using A Postprocessor, Jitter Metastability, Tree-based Interleaver & Low-power CMOS inverter Circuit prototype technology: An Efficient Analysis
Abstract: TRNGs (True Random Number Generators) are cryptographic primitives that generate random numbers for critical operations. The goal of this study is to create a TRNG using a ring oscillator, analyse different calibration generating ways using VHDL spice simulation, and investigate the TRNG's essential design features, such as area, entropy, and power/energy consumption, using suggested and published methods. Random ones and zeros are produced using RO jitter and DCM frequency fluctuations. …
Published in Journal of Microcontroller Engineering and Applications · Vol. 10, Issue 1, 2023 · pp. 66–76 Read article
-
Power-delay Product Optimal Design of Sequential Circuits Using Carbon Nanotubes
Abstract: This paper presents a power-aware high-performance design of ternary combinational and sequential circuits based on carbon nanotube field effect transistor (CNFET) using ternary logic. Carbon nanotube based field effect transistor (CNFET) are being studied extensively as a possible and promising choice for nanoscale integration and as successor to complementary metal oxide semiconductor (CMOS) devices. Ternary logic circuit has attracted substantial interest due to its simplicity, energy efficiency, and reduced interconnect …
Published in Journal of VLSI Design Tools and Technology · Vol. 3, Issue 3, 2013 Read article
-
An Overview on Quantum dot technology in Temperature sensor design
Abstract: Quantumdot (QD) thermometry harnesses the sizedependent electronic structure of semiconductor nanocrystals to translate minute temperature variations into robust optical signals. In this work we present a systematic design framework for QDbased temperature sensors that integrates (i) bandgap engineering through precise colloidal synthesis, (ii) surfacestate passivation to suppress nonradiative pathways, and (iii) a planar photonicreadout architecture compatible with lowcost, CMOSfriendly fabrication. By exploiting the linear redshift of the photoluminescence (PL) peak …
Published in Journal of Electronic Design Technology · Vol. 17, Issue 1, 2026 · pp. 10–17 Read article
-
Realization of Fourth Order Multifunction Filters Using Operational Transresistance Amplifier
Abstract: Design of analog filters, using single Operational Transresistance Amplifier (OTRA) as the active current mode building block, is presented. Five types of filters have been designed namely Low Pass, High Pass, Band Pass, All pass, and Notch. The order of the proposed filters is four. The theoretical results are verified with PSPICE simulation using 0.5m CMOS process parameters provided by MOSIS (AGILENT). Frequency responses for the presented filters are shown …
Published in Journal of Electronic Design Technology · Vol. 3, Issue 1-3, 2012 · pp. 65–71 Read article
-
Characterization of High Speed Phase Frequency Detector Circuit
Abstract: In this paper the performance of high speed phase frequency detector (PFD) is analysed. A high-speed PFD reduces the power consumption of traditional PFD to 0.423 nW at 1 GHz clock frequency and dead zone to 2 ps. It is suitable for low power applications. A PFD uses only 18 transistors. This PFD operates up to 1 GHz at 1.2 V supply voltage. The proposed architecture of the PFD has …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 1, 2015 · pp. 51–58 Read article
-
Swing Restored Low Power and Area Efficient 8-bit Arithmetic Logic Unit Using Modified Gate Diffusion Input Technique
Abstract: AbstractThe arithmetic logic unit (ALU) is one of the most fundamental operational units in any processor. The ALU is the heart of any system or any processor and the core component of the central processing unit because mainly all the fundamental operations are performed by the help of ALU only. So, it can be defined as the combinational unit that is used to perform its logical and arithmetic units. The …
Published in Journal of Microcontroller Engineering and Applications · Vol. 5, Issue 2, 2018 · pp. 19–29 Read article
-
An Optimized 32 bit Carry Select Adder Using Modified BEC
Abstract: AbstractAdders play a major role in addition of numbers, multiplications and other advanced processors’ design. Among the conventional adder structures, carry select adder is known to be fastest adder. This adder circuit is used for the design of high speed processors. The CSLA adder architecture is such that it is of less power dissipation, area efficient and high speed. CSLA circuit for 8, 16, 32 bits is designed without multiplexer …
Published in Journal of Semiconductor Devices and Circuits · Vol. 5, Issue 2, 2018 · pp. 27–32 Read article
-
Comparative Study of a 32 bit Clock Gated ALU based on Carry Skip Adder and Ripple Carry Adder
Abstract: The ALU is one of the most frequently accessed modules in a CPU and is utilized during most instruction executions. Hence the power consumption of the ALU is a major concern. In this paper a low power 32 bit ALU is designed using VHDL. Lower power consumption is achieved by using clock gating technique than conventional design. A carry skip adder with variable block length is used for the arithmetic …
Published in Journal of VLSI Design Tools and Technology · Vol. 3, Issue 2, 2013 · pp. 6–11 Read article
-
Design of 8 Bit High Speed Pipelined ADC
Abstract: High-speed, medium-resolution, analog-to-digital converters (ADCs) are important building blocks in many electronic applications. The demand for high-speed, medium resolution, low power ADCs is satisfied by various ADC architectures like folding, flsubranging, pipeline etc. Of these, pipeline architecture has proven to be the most efficient for applications such as digital communication systems, data acquisition systems and video systems. Pipelined ADC offer attractive combination of high-speed, high-accuracy and low power consumption, which …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 2, 2015 · pp. 71–80 Read article
-
Design of Slew Aware Clock Distribution Network for Ultra Low Power Sub-threshold Applications
Abstract: Clock distribution network consumes significant amount of power due to its high switching activity. The high power consumption issue can be satisfactorily addressed by the sub-threshold operation of device, however at the cost of degraded performance and magnified variability. This paper investigates the suitability of conventional clock distribution network for sub-threshold regime and proposes a novel strategy of having an optimized uniform H-tree with a pair of buffer only at …
Published in Journal of VLSI Design Tools and Technology · Vol. 9, Issue 1, 2019 · pp. 22–37 Read article
-
Recording of Surface-Driven Laminar Flow in Dual Sudden Expansion Microchannel of a Single SU-8 based Glass Microfluidic Device
Abstract: In this work, the SU-8 based glass microfluidic device is fabricated by maskless lithography and indirect bonding technique. A dual sudden expansion microchannel is designed and fabricated inside this fabricated glass microfluidic device. Dyed water is prepared as working liquid by mixing commercially available food dye with distilled water. The surface-driven laminar flow of dyed water inside the fabricated microchannel is recorded by a CMOS camera. This experimental work is …
Published in Recent Trends in Fluid Mechanics · Vol. 7, Issue 1, 2020 · pp. 24–27 Read article
-
Semiconductor Physics and Micron Scale Fluid Mechanics towards the Microelectromechanical Systems Associated with Nanotechnology
Abstract: Interrelations among semiconductor physics, microfluidics, nanofluidics and nanotechnology are briefly described. A single microchannel bend is designed and fabricated by author using the maskless lithography, hot embossing lithography and direct bonding. Dyed water is the selected and prepared working liquid in this work. Surface-driven (passive) capillary flow of working liquid is recorded in the fabricated microchannel bend using a CMOS camera. This work may be useful in applied chemistry.
Published in Research & Reviews : Journal of Physics Read article
-
Design and Implementation of Low Power and High Speed 10T SRAM with High SNM
Abstract: The project introduces a low standby power 10T (LP10T) SRAM cell that focuses on achieving high read stability and write-ability while minimizing power consumption. The LP10T SRAM cell utilizes a strong cross-coupled structure that combines a standard inverter with a stacked transistor and a Schmitt-trigger inverter with a double-length pull-up transistor. One of the key advantages of the LP10T SRAM cell is that it separates the read path from the …
Published in Journal of Microcontroller Engineering and Applications · Vol. 10, Issue 1, 2023 · pp. 40–65 Read article
-
A Reliable Low Standby Power 6T SRAM Cell
Abstract: The project introduces a low standby power 10T (LP10T) SRAM cell that focuses on achieving high read stability and write-ability while minimizing power consumption. The LP10T SRAM cell uses a robust cross-coupled design that combines a Schmitt-trigger inverter with a double-length pull-up transistor and a regular inverter with a stacking transistor. One of the key advantages of the LP10T SRAM cell is that it separates the read path from the …
Published in Journal of VLSI Design Tools and Technology · Vol. 13, Issue 1, 2023 · pp. 33–59 Read article