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55 articles for “using Xilinx”
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Design and Analysis of MAC Unit Using Single Precision Floating Point Vedic Multiplier
Abstract: Multiplication and accumulation are the basic operations which are important in several microprocessors and digital signal processing (DSP) applications to execute dedicated algorithms. Developing high speed MAC is essential for real time DSP application. The MAC unit determines the speed of the overall system and it lies in the critical path. As the demand for high speed design is continuously increasing, the studies related to the field of multipliers and …
Published in Journal of VLSI Design Tools and Technology · Vol. 8, Issue 3, 2018 · pp. 28–35 Read article
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FPGA Implementation of Cryptographic Algorithm for Internet of Things (IoT)
Abstract: Internet of Things (IoT) is an advanced version of internet where it is not just the mobile phones and computers that is connected to internet but also the other electronic objects that get connected to it. IoT describes a system where items in the physical world, and sensors within or attached to these items, are connected to the internet via wireless and wired internet connections. These sensors can use various …
Published in Journal of Web Engineering & Technology · Vol. 3, Issue 2, 2016 · pp. 28–34 Read article
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Implementation of Edge Detection Algorithm on FPGA using Hardware Software Co-simulation
Abstract: Image processing is one of the most booming research areas in modern days. Every modern device incorporates image processing in one or the other way. Most of the image processing algorithms start with basic edge detection. The performance of the edge detection can be improved using state of art FPGA devices. Implementation using field programmable gate arrays (FPGA) speeds up the processing of edge detection algorithms. The paper discusses the …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 1, 2016 · pp. 55–61 Read article
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Different Compressor Adders
Abstract: AbstractMultipliers are one of the main blocks which decide the circuit performance as well as computation speed. In multiplication, addition of partial products contributes most to the circuit delay, power, and area. In this project, compressor adders are used to reduce this delay. Hence, compressors are a major part of the multiplier circuit that decides the overall speed of the system. For high-speed processing and higher systems, a huge number …
Published in Journal of Semiconductor Devices and Circuits · Vol. 5, Issue 2, 2018 · pp. 19–26 Read article
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FPGA Implementation of LDPC Codes
Abstract: AbstractLow Density Parity Check (LDPC) are the linear error correction codes for amendment of mistakes, a technique of transmitting the messages over the noisy channel. With lieu- Shannon’s controlled implementation and typically parallel execution of plan, low-density parity check codes are mainly executed at enquire and well-designed area of applications. Bipartite graph is used for development of LDPC codes. LDPC being limit stirring in the direction of codes which means …
Published in Journal of Telecommunication, Switching Systems and Networks · Vol. 5, Issue 1, 2018 · pp. 21–28 Read article
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Design and Implementation of Low Latency 16-bit Full Adder
Abstract: In the new age world, modern technology has vast applications in various fields of engineering, medicine, and others. Digital electronics processing and systems play a vital role in the analysis and computation of data representation. Electronic systems have gradually become faster and smaller scale. The primary structural element of any modern ALU-based processor is an adder. Addition is a well-known extremely basic function that is employed in nearly all computing …
Published in Journal of VLSI Design Tools and Technology · Vol. 14, Issue 3, 2024 · pp. 21–31 Read article
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Low-Power Reconfigurable Digital Filter Design Using FPGA for IoT Edge Devices
Abstract: The rapid evolution of the Internet of Things (IoT) has led to an exponential increase in the deployment of edge devices that continuously process real-time sensor data under strict power, latency, and computational constraints. Digital filtering remains a critical operation in these devices, supporting tasks such as noise removal, data conditioning, and feature extraction for intelligent decision-making. However, conventional filter implementations on microcontrollers or fixed digital signal processors often struggle …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 3, Issue 2, 2025 · pp. 23–34 Read article
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A Novel Design for High Speed & Area Efficient Compressor Based Vedic Multiplier
Abstract: Multipliers are the most important part in any arithmetic and logic unit, AbstractMultipliers are the most important part in any arithmetic and logic unit, accumulators and digital signal processors. Due to the increasing constraints on delay, the design of faster multipliers is emphasized. Among several multipliers, Vedic multipliers are preferred for their speed of operation. Here the proposed Vedic multiplication techniques are based on “URDHVA TIRYAKBHYAM” a fast and efficient …
Published in Journal of Microelectronics and Solid State Devices · Vol. 5, Issue 3, 2018 · pp. 1–10 Read article
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A Reliable Routing Architecture and Algorithm for Network-on-Chip
Abstract: The Network-on-Chip (NoC) is Network-version of System-on-Chip (SoC) means that on-chip communication through packet based networks. In NOC topology, routing algorithm and switching are main terminology. The routing algorithm is one of the key factors in NoC architecture. The routing algorithm which defines as the path taken by a packet between the source and the destination. The paper proposes a novel algorithm for a Network-on-Chip, which is based on packet …
Published in Journal of Electronic Design Technology · Vol. 6, Issue 3, 2015 · pp. 40–48 Read article
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Study and analysis of the Double Data Rate SDRAM Controller for High-speed Interfacing with Processing Device
Abstract: A real-time embedded system must now manage many programs running concurrently. Increased Data Rate Because of its burst access, speed, and pipeline features, synchronous DRAM is a typical memory-building material. DDR transfers are performed using synchronous dynamic access memory. The memory controller must be set with a pipelined design for various applications and systems to perform effectively. The purpose of this study is to design a DRAM controller that will …
Published in Journal of VLSI Design Tools and Technology · Vol. 14, Issue 1, 2024 · pp. 8–13 Read article
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Hardware Implementation of Configurable Multi Image Fusion
Abstract: Multifocus images make it difficult to describe a scene accurately. Hence, the fusion of two or more images forms a good solution in order to obtain a new image containing more appropriate description of the scene than any of the input images. This paper presents a method of image fusion which uses stationary wavelet transform and fuzzy logic. By overcoming the disadvantages of discrete wavelet transform such as downsampling and …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 1, 2016 · pp. 6–15 Read article
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Implementation of UART with CALBO
Abstract: The increasing growth of submicron technology has resulted in the difficulty of VLSI testing for designers who always look for simple and cost effective logic structure to realize a complex function. Thus Automatic Testing Equipment (ATE) is becoming costly process for testing. To reduce the cost of testing the chips, Built in Self-Test (BIST) has emerged as a cheaper alternative. BIST is a design technique that allows the chip to …
Published in Journal of Microelectronics and Solid State Devices · Vol. 2, Issue 1, 2015 · pp. 6–12 Read article
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An Area Delay Optimized Carry-Select Adder
Abstract: In arithmetic and logic unit of digital signal processor (DSP), adder is the important hardware unit. Carry select adder (CSLA) is the best example of the adder used in DSP and it is widely used in many data processors to increase speed. So, the adder performance affects the overall system-performance. The Regular Square root (SQRT) CSLA consists of two Ripple Carry Adders (RCA), so it consumes more area due to …
Published in Journal of VLSI Design Tools and Technology · Vol. 8, Issue 3, 2018 · pp. 10–14 Read article
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A Review on Comparison of Vedic Multipliers Using Various Types of Adder Topologies
Abstract: Abstract: This paper examines the displays of comparison of Vedic multipliers using various adders. In the design of most high-performance systems such as FIR filters, image processing, microprocessors multipliers are the integral components and multiplication is the important fundamental function in arithmetic operations. Multiplication is the most important job in signal processing apps for numerical operations. Since speed in the multiplication procedure is dependably a must, velocity increases can be …
Published in Journal of Operating Systems Development & Trends · Vol. 6, Issue 3, 2019 · pp. 1–8 Read article
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Design of 16-bit Pipelined RISC Processor
Abstract: This paper presents the design of efficient and high throughput 16-bit pipelined RISC Processor. The design is challenge with the pipelined stall problem, speed with external memory, coding density and clock frequency for cost effectiveness and higher performance processor design. Paper describes about the architecture, programming model, synthesis results and analysis of the design. The presented design has throughput ~167 MIPS at 500 MHz, which shows better performance at a …
Published in Journal of VLSI Design Tools and Technology · Vol. 2, Issue 1-2-3, 2012 · pp. 32–37 Read article
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Implementation of Floating Point Multiplier Using Dadda Algorithm
Abstract: Floating point multiplication is very useful in all the computation applications like in arithmetic operation, DSP application etc. To achieve higher speed of the mantissa, multiplication is done using Dadda multiplier which works on the basis of Dadda algorithm. Through this architecture we gain high speed with a maximum frequency and also reduce the number of gates compared to existing multipliers; and through floating point format it is possible to …
Published in Journal of Multimedia Technology & Recent Advancements · Vol. 3, Issue 1, 2016 · pp. 16–22 Read article
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Real Time FPGA-based Embedded Architecture of Audio Compression and Decompression Core for Multimedia System
Abstract: A multimedia system links images and audio to distribute and transmit information to users. These images and audio data have to be compressed for raising capacity of storing and processing tasks in real time without losing the required information. This paper introduces an audio processing unit by using the FPGA hardware board. This is a complete Embedded system where the audio compression and decompression core is firstly described as a …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 1, 2015 · pp. 34–44 Read article
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Design of FPGA Based ALU Using Reversible Logic Gates
Abstract: Reversible or information misfortune less circuits has applications in computerized signal handling, correspondence, PC design and nanotechnology. Reversible technique is utilized to minimize heat that happens in traditional circuits by keeping the loss of data. This paper proposes a reversible configuration of an ALU. This ALU comprises of eight operations, five are of arithmetic category and three are from logical category operations. An arithmetic operations incorporate add, sub, increase by …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 3, 2016 · pp. 15–21 Read article
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High Throughput LMS Adaptive Filter Architectures using Pipelining and Parallel Processing
Abstract: AbstractIn this paper, a study on existing designs of adaptive filter based on LMS algorithm is done. The primary aim is to reduce the critical path delay and thereby improve throughput. The excess use of multipliers or the lack of a time efficient one and longer cycle periods reduces the effectiveness of any adaptive filter implementation. Here, a simple and highly time efficient Vedic multiplier is used in the implementation …
Published in Journal of Microelectronics and Solid State Devices · Vol. 5, Issue 2, 2018 · pp. 11–19 Read article
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Impact of Xilinx ISE Design Suite’s MAP and Generate Programming Optimization Settings on FPGAs Bitstream Size
Abstract: AbstractIn SRAM based FPGA configuration bitstream resides in configuration memory. Bitstream contains information of CLBs, IOBs and logic interconnects. With increase in complexity of design, size of bitstream increases. Hence if size of bitstream is reduced, less configuration memory required. CAD tools used in FPGA based design has different settings which affects logic capacity, performance speed, resource utilization, power consumption, area required for placing designs etc. In this paper, we …
Published in Journal of Electronic Design Technology · Vol. 9, Issue 1, 2018 · pp. 1–8 Read article