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168 articles for “reduced delay”
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Design and Implementation of Low Power Area Effective 2×4 Decoder for SARM Applications Using 16 nm Technology.
Abstract: This project involves analysis of Modified Mixed Logic Design abbreviated as MMLD which includes following design logics: Complementary Metal Oxide Semiconductor abbreviated to CMOS logic design, Gate Diffusion Input abbreviated as GDI technique, and Dual Value Logic called as DVL. Two logic styles are used in this paper study to reduce power dissipation and delay time which are fourteen 14-transistor and fifteen 15-transistor decoders. Every situation requires the use of …
Published in Journal of Semiconductor Devices and Circuits · Vol. 10, Issue 1, 2024 · pp. 24–36 Read article
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Design And Optimization Of High-Speed Array Multiplier
Abstract: An array multiplier is a digital circuit used for the rapid multiplication of binary numbers. It employs an array of logic gates to generate partial products concurrently, significantly enhancing speed. The array structure divides the multiplication task into smaller, parallel processes, allowing for efficient parallel processing of multiple bits. Each cell within the array manages specific bit-level multiplications, and their results are summed to produce the final product. This parallel …
Published in Journal of Microelectronics and Solid State Devices · Vol. 11, Issue 3, 2024 Read article
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THE REGULATORY ROLE OF FOOD SPICES AGAINST LIPID PEROXIDATION IN MEAT PRODUCTS
Abstract: Spices are plant-based materials used for enhancing the flavor, taste and aroma of meat and have been employed in cooking and meat processing for many decade. Interestingly, some of these spices have found relevance in meat preservation as they not only enhance the flavor and taste of meat product but can also reduce meat spoilage. One of the major causes of meat spoilage outside those induced by microbes is Lipid …
Published in Research & Reviews : Journal of Food Science & Technology · Vol. 13, Issue 3, 2024 · pp. 21–25 Read article
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Photonic-Assisted Spintronic Solid-State Switching Model for High-Speed Memory Devices
Abstract: The rapid advancement of high-speed computing and data-centric applications has intensified the demand for energy-efficient and ultra-fast memory technologies. This paper proposes a Photonic-Assisted Spintronic Solid-State Switching Model for next-generation high-speed memory devices. The proposed framework integrates photonic excitation mechanisms with spintronic switching dynamics to enhance data transfer speed, minimize switching delay, and reduce power dissipation in solid-state memory architectures. By combining optical pulse-assisted spin polarization with magnetic tunnel junction-based …
Published in International Journal of Solid State Innovations & Research · Vol. 4, Issue 1, 2026 Read article
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A Novel Approach of Traffic Management in Software Defined Networking Using Internal Controller
Abstract: The complex structure of the current computer networks causes problems in network scalability and management and makes it hard and time-consuming to implement general policies. A new architecture called Software Defined Network (SDN) has been developed to address these problems and challenges. One of the most important issues in SDNs is traffic engineering, which is a good criterion for network performance evaluation. After introducing SDNs and examining traffic engineering and …
Published in Journal of Communication Engineering & Systems · Vol. 10, Issue 1, 2020 · pp. 22–31 Read article
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Clinical study on dual plating for delayed unions and nonunions of distal 1/3 and diaphyseal-metaphyseal transition of humerus
Abstract: Background: The best treatment for delayed union and non-union at distal 1/3 and metaphyseal-diaphyseal transition of humerus is not well established. We collected retrospective and prospective outcomes data for patients undergoing open reduction and internal fixation for delayed union and non-union of distal 1/3 and metaphyseal-diaphyseal transition of humerus with use of conventional mono-lateral or dual plating. Methods and Material: Over a 2-year period, 35 patients underwent open reduction and …
Published in Research and Reviews : Journal of Surgery · Vol. 9, Issue 2, 2020 · pp. 10–15 Read article
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High Speed and Low Power Basic Digital Logic Gates, Half-Adder and Full-Adder Using Modified Gate Diffusion Input Technology
Abstract: In this paper, modified gate diffusion input (MGDI) technology has been used for the design and implementation of digital integrated circuits (ICs). In today’s digital world, IC plays a vital role in high-performance computing, communication, and many consumer electronics. IC manufacturing technology has scaled down to smaller device dimensions. This scaling has a great impact on the design of digital ICs. The main objective of the IC manufacturing technology is …
Published in Journal of VLSI Design Tools and Technology · Vol. 8, Issue 1, 2018 · pp. 34–42 Read article
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A Novel Design for Power Reduction in Arithmetic Circuits using MTCMOS Technology
Abstract: In CMOS logic circuits, the reduction in the threshold voltage due to voltage scaling leads to increase in the subthreshold leakage current and hence static power dissipation. Although power consumption is important for modern VLSI design, operation speed and occupied area are still the main requirements of the VLSI design. Multi threshold voltage CMOS (MTCMOS) technology is a good solution which provides a high performance and low-power design without any …
Published in Journal of VLSI Design Tools and Technology · Vol. 4, Issue 1, 2014 · pp. 1–7 Read article
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Economic Load Dispatch using GAMS for 20 bus Rapid Transit Vehicular System
Abstract: This paper investigates a 20-bus system smart grid for economic load dispatch using GAMS software which is used for future rapid transit vehicles. Rapid transit is the need of the hour of the emerging vehicular technologies. If we are trying to understand the various transit systems such as buses and trains and again the classification of light rail, metro and fast and bullet trains running on a DC/AC system, it …
Published in Trends in Electrical Engineering · Vol. 13, Issue 3, 2023 · pp. 1–6 Read article
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Design and Performance Analysis of Full Adder Cell using FinFET Technique at 32nm Technology
Abstract: AbstractIn this paper, discussed is the comparative analysis of complementary MOS (CMOS) and dual gate-FinFET (fin shaped field effect transistor) based full adder cell design. To reduce the average power, average current and maximum current of 1-bit full adder circuit a new high DG-FinFET technique is presented. Use of double-gate FinFET technology provides low leakage and high performance operation. For MOSFET transistor model, a predictive technology model (PTM) BSIM4 and …
Published in Journal of Microelectronics and Solid State Devices · Vol. 4, Issue 3, 2017 · pp. 1–8 Read article
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A Novel Logic Styles used for Leakage Power Reduction in MOS Integrated Circuit
Abstract: Modified constant delay logic style and clocked logic style is defined by comparing their result. In this paper, a design technique has been proposed which reduces the power dissipation. The design and implementation of full adder and ripple carry adder with constant delay logic. The leakage power has become a serious concern in CMOS technologies that has been solved by the MCD and clocked logic style. Constant delay logic style …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 1, 2016 · pp. 1–5 Read article
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Classification of Plant Leaf Diseases Using Deep Learning Concepts
Abstract: Agriculture is vital to the economy of a country like India, where 70% of the workforce is employed in this sector. Plants suffering from illnesses experience a significant reduction in output. Delays in the identification of plant diseases lead to decreased yield and plant mortality. The cost of manufacturing is increased since it takes a big number of experts to manually detect plant diseases over several acres of land. The …
Published in Journal of Image Processing & Pattern Recognition Progress · Vol. 12, Issue 3, 2025 · pp. 46–55 Read article
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Single Bit Low-Power High-Speed Full Adder
Abstract: This paper presents a high-speed low-power full adder cells that lead to have a reduced power-delay product (PDP). A comparison against other full-adder structure as having low PDP, in terms of speed, power consumption and area of cells is carried out. This paper contains, a hybrid 1-bit full adder design employing both complementary metal-oxide semiconductor (CMOS) and transmission gate logic styles. First implemented was the design for 1 bit then …
Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 3, 2017 · pp. 55–60 Read article
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Single Bit Low-Power High-Speed Full Adder
Abstract: This paper presents a high-speed low-power full adder cells that lead to have a reduced power-delay product (PDP). A comparison against other full-adder structure as having low PDP, in terms of speed, power consumption and area of cells is carried out. This paper contains, a hybrid 1-bit full adder design employing both complementary metal-oxide semiconductor (CMOS) and transmission gate logic styles. First implemented was the design for 1 bit then …
Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 2, 2017 · pp. 55–60 Read article
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A Nobel Approach of Designing A 4 Bit Carry Skip Adder Using Reversible Logic
Abstract: This paper presents a method to designing Various Adder Circuits using CMOS Logic Style for Energy-Efficient Arithmetic Applications. We present Ripple Carry Adder, Carry Bypass Adder, Carry Look Ahead Adder and Carry Skip Adder in CMOS logic styles that lead to have reduced power-delay product (PDP). We executes a comparison against each other adders which finally provide result as having a low PDP, with reference to power consumption, speed and …
Published in Journal of VLSI Design Tools and Technology · Vol. 11, Issue 2, 2021 · pp. 24–34 Read article
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Design and Implementation of Carry Select Adder based On Wallace tree Multiplier using Adiabatic Logic
Abstract: The Wallace tree multiplier construction using a carry select adder (CSA) and this paper discusses adiabaticlogic. The proposed design aims to reduce power consumption while maintaining high performance.Adiabatic logic is employed to reduce power dissipation by recycling energy during the logic transitions. TheWallace tree multiplier is used to perform fast multiplication of two large numbers by breaking down themultiplication process into smaller sub-tasks. The CSA is used as the adder …
Published in Journal of VLSI Design Tools and Technology · Vol. 13, Issue 2, 2023 · pp. 21–31 Read article
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A 32-Bit Booth Multiplier Design Using GDI Logic Style
Abstract: Gate diffusion input (GDI) is the newest technology of designing a low-power digital combinational circuit. This logic allows reducing power dissipation, delay and area of any digital logic circuit. The gate diffusion input logic allows implementation of a wide range of any complex logic function. These functions can be realized using only two transistors. This technique is preferred for designing fast using less number of transistors while improving logic level …
Published in Trends in Electrical Engineering · Vol. 5, Issue 3, 2015 · pp. 1–5 Read article
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Delay Analysis for VLSI Interconnect’s Circuits
Abstract: This research work has been comprised of three parts. The first part deals with the implementation and estimation for the delay of an inverter and study of the influence of the delay variations with the increased size of the inverter. In this modern era of VLSI integrated circuits, interconnect’s delay majorly influences the device delay. The second phase of the work emphasizes on the realization of the interconnect delay and …
Published in Journal of Electronic Design Technology · Vol. 6, Issue 3, 2015 · pp. 25–32 Read article
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High Throughput LMS Adaptive Filter Architectures using Pipelining and Parallel Processing
Abstract: AbstractIn this paper, a study on existing designs of adaptive filter based on LMS algorithm is done. The primary aim is to reduce the critical path delay and thereby improve throughput. The excess use of multipliers or the lack of a time efficient one and longer cycle periods reduces the effectiveness of any adaptive filter implementation. Here, a simple and highly time efficient Vedic multiplier is used in the implementation …
Published in Journal of Microelectronics and Solid State Devices · Vol. 5, Issue 2, 2018 · pp. 11–19 Read article
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Design and Implementation of 256-bit Vedic Multiplier on Reconfigurable Platform
Abstract: Multiplication is a fundamental arithmetic operation in digital signal processing and embedded systems. Traditional multiplier architectures often suffer from increased latency and resource utilization when scaled to higher bit widths. Vedic Mathematics, an ancient Indian technique, offers a novel and efficient alternative. This paper presents the design and implementation of a 256-bit Vedic multiplier using the Urdhva Tiryakbhyam Sutra on a reconfigurable hardware platform, specifically FPGA. The proposed architecture decomposes …
Published in Journal of Materials & Metallurgical Engineering · Vol. 15, Issue 3, 2025 · pp. 56–65 Read article