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156 articles for “gating design”
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Design of Optimized Full Adder using Noise-Mitigation Techniques and Power Gating
Abstract: With the advent of nanoscale technology, a new era of power consumption, speed, and reliability challenges for traditional static CMOS logic has begun. To solve these problems, dynamic logic families—particularly domino logic—have emerged as potent substitutes that offer quicker processing speeds and lower power consumption. The design and optimization of a full adder circuit using domino logic is shown in this study. A dynamic domino logic technique is used to …
Published in Journal of Microelectronics and Solid State Devices · Vol. 11, Issue 3, 2024 · pp. 1–6 Read article
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Some Investigations with Ultra High Speed Low Power All Optical digital Logic Gates
Abstract: AbstractThis paper illustrates design for an all-optical optical inverter and universal digital logic NAND gate using NRZ format, realized by MZI structure. Miscellaneous evaluations have been done to examine the designs performance in terms of their generated output waveforms. Simulations have been done for significant design parameters as chirp factor, laser power and bit error rate at different data-rates. Optical Logical gate outputs have been verified. It showed good design …
Published in Trends in Opto-electro & Optical Communication · Vol. 8, Issue 3, 2018 · pp. 17–30 Read article
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Modification of gating System of Ball Valve Component using Soft-cast Simulation
Abstract: There are two main important considerations in castings are quality of the casting and yielding of the casting due to which scrape of material will reduce. Production of good quality casting mainly depends upon the gating system. In casting process gating and risering system has direct effect on its quality. Generally, many industries follow the trial and error method for casting process which is not economical for foundries for long …
Published in Trends in Mechanical Engineering & Technology · Vol. 7, Issue 3, 2017 · pp. 79–85 Read article
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Improvement of Design Issues in FinFET based Design Techniques for XOR and XNOR Circuits at 45 nm Technology
Abstract: The scaling of conventional CMOS circuit inclines to the short channel effect due to leakage current increase in the circuit. To minimize the short channel effect, FINFET can be used in place of conventional CMOS circuits. This paper demonstrates comparative performance study of high speed, low power and low voltage on XOR and XNOR digital circuit. This paper assesses and compares the performance of XOR and XNOR logic circuits. This …
Published in Journal of Electronic Design Technology · Vol. 5, Issue 1, 2014 · pp. 22–35 Read article
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Memristor based Material Implication Logic for Implementation of Basic logic Gates and Circuits
Abstract: A physical memristor was realized a few years back by Hewlett Packard labs. Instantly it became the topic of interest for many scientists and researchers. Memristor has joined resistor, capacitor and inductor in the list of basic two-terminal passive circuit elements. Field Programmable Gate Arrays (FPGAs) have become a major choice of technology for the implementation of various digital circuits because they offer various features such as quick time to …
Published in Journal of VLSI Design Tools and Technology · Vol. 8, Issue 1, 2018 · pp. 17–22 Read article
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Design and Simulation of 4-bit Multiplier using Carry Look-Ahead Adder at Transistor Level
Abstract: Multiplication is a basic operation performed in the Arithmetic Logic Unit, Digital signal processing, Floating-point unit and Application specific integrated circuits. This paper deals with the design and simulation of the 4-bit multiplier using a carry look-ahead adder at the transistor level. The total design process involves hierarchical implementation. Where the basic gate operations like AND, OR, NOT, and XOR are repeatedly used for designing the entire circuit. So, the …
Published in Journal of VLSI Design Tools and Technology · Vol. 11, Issue 3, 2021 · pp. 10–18 Read article
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RTL-to-GDSII Flow Optimization for Low-Power 32-bit RISC-V Processor
Abstract: This paper presents the implementation and optimization of a 32-bit RISC-V processor, transitioning from Register Transfer Level (RTL) design to final GDSII using Synopsys Fusion Compiler over 32nm technology node. The processor architecture is based on the RV32I base instruction set and incorporates a 5-stage pipeline to achieve a balanced trade-off between performance and design complexity. The design methodology involved RTL synthesis, gate-level netlist generation, and successive physical design stages …
Published in Journal of VLSI Design Tools and Technology · Vol. 15, Issue 3, 2025 · pp. 1–10 Read article
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A 32-Bit Booth Multiplier Design Using GDI Logic Style
Abstract: Gate diffusion input (GDI) is the newest technology of designing a low-power digital combinational circuit. This logic allows reducing power dissipation, delay and area of any digital logic circuit. The gate diffusion input logic allows implementation of a wide range of any complex logic function. These functions can be realized using only two transistors. This technique is preferred for designing fast using less number of transistors while improving logic level …
Published in Trends in Electrical Engineering · Vol. 5, Issue 3, 2015 · pp. 1–5 Read article
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Simulation of Three Section Multilevel Inverter with Reduced Range of Switches
Abstract: Because of high generation development, the demand and excellent of electric strength ishigher than earlier than. Furthermore, due to the advancement of semiconductor, thespecification of electricity devices and strength conversion method turn out to be stricter. Oneof the energy converters that may remodel DC to AC is called inverter. An inverter is the intermedium to transmit the electricity to other electric device such as an uninterruptibleelectricity supply, servo motor, air-conditioner …
Published in Journal of VLSI Design Tools and Technology · Vol. 10, Issue 1, 2020 · pp. 15–36 Read article
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Water Modelling of Gating System
Abstract: Water modelling of a gating system in a foundry can be used to improve the quality of the castings produced to thrive in the global competitive environment, minimize the cycle time, reduce the cost, as well as meet its delivery times. So, from a customer and an economic point of view foundries cannot afford production of series of trial castings with routine changes in the gating system and choose the …
Published in Journal of Experimental & Applied Mechanics · Vol. 11, Issue 2, 2020 · pp. 1–3 Read article
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Autonomous Optimization, Method Design of Casting and Its Experimental Validation: A Case Study
Abstract: The metal casting is a complicated but a mass production manufacturing technique. But on the otherhand, the chances of casting rejection are also more if proper attention is not made at every stage ofcasting production. In the metal casting process, higher yield and minimum defects level are expectedby the foundry industries. In the present global and competitive world metal casting industries needsto perform efficiently with a reduction in rejections. This …
Published in Trends in Machine design · Vol. 8, Issue 1, 2021 · pp. 1–10 Read article
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Proposed System: Quantum Computing Processor Based on Linear Number Relation
Abstract: This paper details the design and implementation of a specialized quantum processor tailored for efficiently evaluating custom mathematical formulas. Optimized to perform a specific set of arithmetic and logical operations, this processor delivers a stable and high-performance computing platform. Unlike general-purpose quantum processors, which are designed for versatility across a wide range of algorithms, this dedicated processor aims to enhance performance and accuracy for a targeted set of tasks. The …
Published in Recent Trends in Parallel Computing · Vol. 11, Issue 3, 2024 · pp. 24–32 Read article
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Performance Analysis of Complimentary Pass Transistor Logic Based Multiplexer Using Dual-gate FinFET Technology
Abstract: AbstractThis paper presents the design and analysis of double gate FinFET complimentary pass transistor logic (CPL) multiplexer. The circuit of multiplexer (MUX) using CPL is used for comparison of performance parameters like average power consumption, rise/fall time, delay, slew rate, PDP and EDP. Multiplexer is a digital circuit, it has inputs and select line; select lines are used for select input lines to transfer data to the output end. The …
Published in Journal of Microelectronics and Solid State Devices · Vol. 5, Issue 1, 2018 · pp. 41–48 Read article
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High Speed and Low Power Basic Digital Logic Gates, Half-Adder and Full-Adder Using Modified Gate Diffusion Input Technology
Abstract: In this paper, modified gate diffusion input (MGDI) technology has been used for the design and implementation of digital integrated circuits (ICs). In today’s digital world, IC plays a vital role in high-performance computing, communication, and many consumer electronics. IC manufacturing technology has scaled down to smaller device dimensions. This scaling has a great impact on the design of digital ICs. The main objective of the IC manufacturing technology is …
Published in Journal of VLSI Design Tools and Technology · Vol. 8, Issue 1, 2018 · pp. 34–42 Read article
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QCA-based Implementation of Budget-friendly and Energy-Efficient Exclusive-OR/Exclusive-NOR Gates
Abstract: Quantum-dot cellular automata (QCA) is a novel nanoscale computational approach that proposes reduced dimensions, lower power consumption, increased speed, and deliberate design as a solution to the scaling challenge associated with CMOS technique. QCA is a nascent nanotechnology that utilizes the Coulomb repulsion principle. Quantum computing has emerged as a highly effective paradigm for the creation of energy-efficient hardware at the nanoscale. This article presents implementation of a very efficient …
Published in International Journal of Electro-Mechanics and Material Behaviour · Vol. 1, Issue 2, 2023 · pp. 1–6 Read article
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Design of Fault Tolerant Reversible Comparator
Abstract: Reversible circuits have proved its significance in the synthesis of circuits having their important role in nanotechnology, quantum computing, low power CMOS Design, cryptography and Bioinformatics. The Reversible Gates can be further made more beneficial if they prove themselves to be Fault Tolerant i.e. where errors can be detected and corrected at the same time. This Paper considers parity preserving technique for making Reversible circuits Fault Tolerant. Parity Preserving Gates …
Published in Journal of Semiconductor Devices and Circuits · Vol. 6, Issue 2, 2019 · pp. 13–17 Read article
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Comparative Study of a 32 bit Clock Gated ALU based on Carry Skip Adder and Ripple Carry Adder
Abstract: The ALU is one of the most frequently accessed modules in a CPU and is utilized during most instruction executions. Hence the power consumption of the ALU is a major concern. In this paper a low power 32 bit ALU is designed using VHDL. Lower power consumption is achieved by using clock gating technique than conventional design. A carry skip adder with variable block length is used for the arithmetic …
Published in Journal of VLSI Design Tools and Technology · Vol. 3, Issue 2, 2013 · pp. 6–11 Read article
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Single Bit Low-Power High-Speed Full Adder
Abstract: This paper presents a high-speed low-power full adder cells that lead to have a reduced power-delay product (PDP). A comparison against other full-adder structure as having low PDP, in terms of speed, power consumption and area of cells is carried out. This paper contains, a hybrid 1-bit full adder design employing both complementary metal-oxide semiconductor (CMOS) and transmission gate logic styles. First implemented was the design for 1 bit then …
Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 3, 2017 · pp. 55–60 Read article
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Single Bit Low-Power High-Speed Full Adder
Abstract: This paper presents a high-speed low-power full adder cells that lead to have a reduced power-delay product (PDP). A comparison against other full-adder structure as having low PDP, in terms of speed, power consumption and area of cells is carried out. This paper contains, a hybrid 1-bit full adder design employing both complementary metal-oxide semiconductor (CMOS) and transmission gate logic styles. First implemented was the design for 1 bit then …
Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 2, 2017 · pp. 55–60 Read article
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A Study of Cycloconverter Gating Sequence and Control Strategy for Various Conversion Topology
Abstract: This paper presents the topology of direct conversion of AC-AC with step down frequency operation. Due to the higher order harmonics, AC conversion always faces difficulty and complex calculation, which affects the output response. Precise controlling and harmonics reduction is much easier using frequency control strategy. In this regards cycloconverter has drawn higher attention in terms of frequency conversion. In this paper, an approach for designing of single phase and …
Published in Trends in Electrical Engineering · Vol. 6, Issue 3, 2016 · pp. 67–77 Read article