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1050 articles for “Multiplication”
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A Novel Current-Mode Quaternary Multiplier with Indian Vedic Architecture
Abstract: A multiplier is a fundamental block of any digital signal processing system. Urdhva Tiryakbhyam sutra, from ancient Indian Vedic mathematics, offers regular and hierarchical multiplier architecture. Alternatively, current-mode multi-valued logic results in reduced circuitry and effective utilization of interconnections. In this paper, a new 4×4 current-mode quaternary Vedic multiplier design is proposed. The multiplier has been simulated using 0.18 µm technology with a power supply of 1 V and a …
Published in Journal of VLSI Design Tools and Technology · Vol. 4, Issue 2, 2014 · pp. 37–46 Read article
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Analysis of Resource Utilization for a Floating-Point Complex Multiplication in FPGA
Abstract: Complex multiplication is an important operation frequently used in the digital signal processing. This paper shows the resource utilization for a complex multiplication on Spartan3E by using a 9 bit floating point numbers. The proposed method clearly shows that resource utilization for complex multiplication is less than the IP cores proposed by the Xilinx Company. More over this paper shows how the significant and the exponent of the floating point …
Published in Journal of VLSI Design Tools and Technology · Vol. 1, Issue 1-2-3, 2011 · pp. 9–14 Read article
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Comparative Analysis of CMOS CNFET and Memristor Based Full Adder Circuits and CMOS Memristor Based Multiplexer Circuits
Abstract: Continued developments in microelectronics technology have led to a myriad of new compute-intensive applications at the micro-edge, such as artificial intelligence and signal and image processing. Multiplication is a crucial arithmetic process in such applications. However, large logic complexities typically seen in traditional multipliers generate combinatorial blocks with long chains of cascaded carry addition. As such, energy efficiency has remained a primary design challenge for these applications, when powered by …
Published in Journal of VLSI Design Tools and Technology · Vol. 12, Issue 2, 2022 · pp. 22–33 Read article
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Design and Implementation of 256-bit Vedic Multiplier on Reconfigurable Platform
Abstract: Multiplication is a fundamental arithmetic operation in digital signal processing and embedded systems. Traditional multiplier architectures often suffer from increased latency and resource utilization when scaled to higher bit widths. Vedic Mathematics, an ancient Indian technique, offers a novel and efficient alternative. This paper presents the design and implementation of a 256-bit Vedic multiplier using the Urdhva Tiryakbhyam Sutra on a reconfigurable hardware platform, specifically FPGA. The proposed architecture decomposes …
Published in Journal of Materials & Metallurgical Engineering · Vol. 15, Issue 3, 2025 · pp. 56–65 Read article
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Investigation of Pass Transistor Logic and CMOS Logic Configuration Based D-Multiplexers
Abstract: Pass Transistor Logic (PTL) arrangement depicts a few rationale families utilized in the plan of incorporated circuits. It lessens the include of transistors utilized making distinctive rationale entryways, by killing excess transistors. The pass transistor is driven by an intermittent clock flag and goes about as an entrance change to ON (1) or OFF (0), contingent upon the information flag. The utilization of pass transistor rationale has brought about noteworthy …
Published in Journal of Microelectronics and Solid State Devices · Vol. 9, Issue 2, 2022 · pp. 1–8 Read article
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Design of Booth Encoded Multi-Modulus {2n-1, 2n, 2n+1} RNS Multiplier
Abstract: Multiplication, a very important arithmetic operation, is finding a great use these days in various applications (especially DSP, multimedia and image processing). Due to advances in technology and increasing needs for high-speed calculations, it has become really necessary and important to design a fast efficient multiplier. A productive method to speed up the multiplication is reduction in the Partial Product (PP) array. In this paper, the design of 8, 16 …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 3, 2016 · pp. 7–14 Read article
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Design and Simulation of 4-bit Multiplier using Carry Look-Ahead Adder at Transistor Level
Abstract: Multiplication is a basic operation performed in the Arithmetic Logic Unit, Digital signal processing, Floating-point unit and Application specific integrated circuits. This paper deals with the design and simulation of the 4-bit multiplier using a carry look-ahead adder at the transistor level. The total design process involves hierarchical implementation. Where the basic gate operations like AND, OR, NOT, and XOR are repeatedly used for designing the entire circuit. So, the …
Published in Journal of VLSI Design Tools and Technology · Vol. 11, Issue 3, 2021 · pp. 10–18 Read article
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Reduced Partial Product Booth Multiplier with An Effective Error Compensation Circuit
Abstract: Reduced partial product Booth multiplier is mainly used in multimedia and digital signal processing (DSP) systems. In this paper, design of reduced partial product (constant-width) Booth multiplier is introduced. Here the least significant bit (LSB) of partial product matrix of Booth multiplier is removed and an error compensation function is derived for reducing truncation error. A simple error compensation circuit (SC generator) is also introduced to reduce the computations that …
Published in Trends in Electrical Engineering · Vol. 5, Issue 2, 2015 · pp. 42–49 Read article
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Serum Hepcidin Status of Sickle Cell Disease Subjects with Multiple Blood Transfusion in Nigeria
Abstract: Objectives: No effective physiological mechanism for excess iron excretion is known in humans. Conditions such as sickle cell disease (SCD), where red blood cell transfusion is a frequently employed therapy can subsequently result in ready accumulation and circulation of exogenous iron as non-transferrin bound iron in tissues with possible impairment of iron homeostasis in them. Aim: The influence of multiple blood transfusions on the patterns of iron homeostasis in correlation …
Published in Research and Reviews: A Journal of Medicine · Vol. 9, Issue 2, 2019 · pp. 1–9 Read article
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An Offline Space Division Multiplexing Based Elastic Optical Network Model with Switching and Modulation Format Adaptation for Flexible Spectrum and Spatial Assignment
Abstract: Abstract: The Space Division Multiplexing (SDM) based Elastic Optical Networks (EONs) (SDM-bEONs) is the proposed solution to both, the required upgradation of the network’s capacity constrained by the non-linear Shannon’s limit and the provisioning needed for the future diverse Internet traffic’s required capacity. With SDM providing ‘space’ as an additional freedom degree, the assignment of resource (i.e., spectrum and space) in the SDM-b-EONs translates into the Routing, Modulation Format, Space, …
Published in Trends in Opto-electro & Optical Communication · Vol. 9, Issue 1, 2019 · pp. 1–23 Read article
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Power and Area - Aware Recursive Multiplier Architecture Utilizing Polymer Composites for Neural Network Acceleration
Abstract: Approximate computing is widely applied in error - tolerant systems as an effective technique to enhance circuit performance by deliberately allowing occasional inaccuracies instead of strictly ensuring precise results for every computation. Among the fundamental building blocks of digital systems, multipliers play a crucial role in signal processing, control systems, and machine learning applications; however, they demand significant power, silicon area, and timing resources. Leveraging error - tolerant approximate multipliers …
Published in Journal of Polymer & Composites · Vol. 14, Issue 1, 2026 · pp. 1320–1337 Read article
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Design and Analysis of Energy-Efficient GDI Cell and Its Impact on Multipliers
Abstract: VLSI design technology suffers from three major issues such as area, speed and power. Among these issues, power is a serious concern that is yet to be considered. So, in this paper, power is concerned more as compared to area and speed. GDI (gate diffusion input) is one of the common techniques used in VLSI design systems to reduce power consumption. Due to its high performance and less area overhead, …
Published in Journal of VLSI Design Tools and Technology · Vol. 4, Issue 2, 2014 · pp. 32–36 Read article
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Design of High Voltage Generation through Cockcroft–Walton Voltage Multiplier Circuit: A Review
Abstract: There are several advantages of High voltage DC (HVDC) system. However, the main limitation of the HVDC system is the generation of HVDC. Therefore, the objective of the paper is to emphasize the design of a high voltage generation through Cockcroft–Walton Voltage multiplier circuit. This paper focus on development in Cockcroft-Walton Voltage multiplier circuit since decades, various other topologies available, designing parameters of Cockcroft–Walton Voltage multiplier circuit. The paper tends …
Published in Journal of Control & Instrumentation · Vol. 11, Issue 3, 2020 · pp. 42–50 Read article
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Comparative Analysis of CMOS CNFET and Memristor Based Full Adder Circuits and CMOS Memristor Based Multiplexer Circuits
Abstract: Continued developments in microelectronics technology have led to a myriad of new compute- intensive applications at the micro-edge, such as artificial intelligence and signal and image processing. Multiplication is a crucial arithmetic process in such applications. However, large logic complexities typically seen in traditional multipliers generate combinatorial blocks with long chains of cascaded carry addition. As such, energy efficiency has remained a primary design challenge for these applications, when powered …
Published in Journal of VLSI Design Tools and Technology Read article
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Three Stage High Step-up Interleaved Boost Converter with Voltage Multiplier Cell
Abstract: In this paper, three stage high step-up interleaved boost converter with three voltage multiplier cells (VMCS) and three state switching cells (3SSC) is proposed. Here an interleaved boost converter is used, as a result higher efficiency and reduced input ripple current is obtained. Also, an additional stage of voltage multiplier i.e., three stages is added so that voltage gain will increase. It reduces switching loss and stress through the devices. …
Published in Journal of Electronic Design Technology · Vol. 5, Issue 1, 2014 · pp. 39–56 Read article
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Phase Noise Reduction in WLAN by Applying Wavelet Packet Multiplexing
Abstract: The IEEE 802.11 standards for wireless Local Area Networks (LANs) commercialized as Wi-Fi are deployed in office and home environments. These systems provide data rates up to 1300 Mbps at 5 GHz and 400 Mbps at 2.4 GHz with physical layer based on OFDM and MIMOOFDM. Traditionally, multiplexing in OFDM is realized using static orthogonal waveforms derived from Fourier transforms. The decoding of the data at receiver is based on …
Published in Journal of Communication Engineering & Systems · Vol. 7, Issue 3, 2017 · pp. 8–15 Read article
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Study and Performance Analysis of Orthogonal Frequency Division Multiplexing with Different Modulation for Rayleigh Channel Model
Abstract: AbstractFor the advancement of wireless communication systems, methods such as MIMO, OFDM and integrating them together as MIMO-OFDM are very useful. OFDM is used in numerous wireless transmission standards nowadays. In OFDM, high rate data stream is divided into low-rate streams which are transmitted together over a number of subcarriers. A broadband and frequency-selective channel are transformed into a multiplicity of parallel narrow-band single channels by the OFDM modulation. By …
Published in Journal of Communication Engineering & Systems · Vol. 9, Issue 2, 2019 · pp. 76–80 Read article
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Simulation of Wavelength Division Multiplexing Based Fiber Optic Link by Using Different Types of Dispersion Compensating Fiber
Abstract: Wavelength division multiplexing (WDM) multiplies various optical signals on a single optical fiber by using different wavelengths of laser light at the transmitter end and demultiplex them into multiple opticalsignal at the receiver end. We want to improve overall system performance and reduced as much as possible the transmission performance influenced by the dispersion, several dispersion compensation technologies are involved. In this paper, we have studied the WDM based fiber …
Published in Trends in Opto-electro & Optical Communication Read article
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Simulation of Wavelength Division Multiplexing Based Fiber Optic Link by Using Different Types of Dispersion Compensating Fiber
Abstract: Wavelength division multiplexing multiplies various optical signals on a single optical fiber by using different wavelengths of laser light at the transmitter end and demultiplex them into multiple optical signal at the receiver end . We want to improve overall system performance and reduced as much as possible the transmission performance influenced by the dispersion, several dispersion compensation technologies are involved. In this paper we have studied the WDM based …
Published in Trends in Opto-electro & Optical Communication · Vol. 11, Issue 1, 2021 · pp. 19–24 Read article
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Wavelength Division Multiplexing in Optical Networks Using Radio Over Fiber
Abstract: AbstractThis paper contains a detailed study about WDM (wavelength division multiplexing) optical networks. The bandwidth, speed and loss of signals in communication have a reason to worry in communication systems; WDM makes the possible solution to resurrect the systems of communications with the help of this technology. The issue emerges when the interest for transfer speed in a fiber optic system surpasses the present limit, without requiring any extra fiber, …
Published in Journal of Communication Engineering & Systems · Vol. 9, Issue 3, 2019 · pp. 12–15 Read article