STM Journals Peer-reviewed research from Consortium e-Learning Network

Journal of Polymer & Composites Original Research Special issue

Power and Area - Aware Recursive Multiplier Architecture Utilizing Polymer Composites for Neural Network Acceleration

  1. Sunkara Bhanu Prakash Department of ECE, Koneru Lakshmaiah Education Foundation, Center for Multi -Core Architecture Computation (C - MAC), Vaddeswaram
  2. Aravindhan Alagarsamy Department of ECE, Koneru Lakshmaiah Education Foundation, Center for Multi - Core Architecture Computation (C - MAC), Vaddeswaram
  3. Pradeep C Department of ECE, Saintgits College of Engineering, Kottukulam Hills, Kottayam
  4. Ann Wesley Mathew Center for Development of Advanced Computing (CDAC), Bengaluru

Abstract

Approximate computing is widely applied in error - tolerant systems as an effective technique to enhance circuit performance by deliberately allowing occasional inaccuracies instead of strictly ensuring precise results for every computation. Among the fundamental building blocks of digital systems, multipliers play a crucial role in signal processing, control systems, and machine learning applications; however, they demand significant power, silicon area, and timing resources. Leveraging error - tolerant approximate multipliers has therefore emerged as an attractive solution for resilient applications such as multimedia processing, data analytics, image and video compression, and artificial intelligence, where perfect numerical accuracy is often not essential for acceptable system - level performance. Despite their foundational importance in digital processing hardware, conventional binary multipliers impose substantial silicon area overhead and energy consumption, which in turn restricts the scalability of high - performance and low - power systems. To overcome these challenges, this work introduces a power - and area - aware recursive multiplier architecture that efficiently exploits the principles of approximate computing. The proposed architecture further leverages the advantages of polymer composite–based electronic platforms, enabling optimized integration under strict power density and thermal constraints. The study primarily focuses on integrating the proposed recursive multiplier into neural network accelerators, where most standard multiply–accumulate operations are always executed in parallel. By significantly reducing power consumption and hardware area while preserving acceptable computational accuracy, the proposed design offers an effective and scalable solution for energy - efficient neural network inference and next - generation intelligent embedded systems.

Keywords

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