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153 articles for “CMOS design”
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Comparative Analysis of High Speed Comparator for A to D Converters
Abstract: In this paper dynamic comparator along with the output buffer stage has been introduced. The simulation is carried out in 130 and 90 nm technologies. The supply voltage for 130 nm is 1.3 V and for 90 nm is 0.9 V. Different analyses for various characteristics of the comparator such as ICMR, delay, offset voltage and power dissipation is carried out in 130 and 90 nm CMOS technology. The comparator …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 2, 2015 · pp. 4–10 Read article
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Modelling and Electrical Characterization of Single Electron Transistor
Abstract: A nano-electronic device with low power consumption, high performance, and quantum effects is the single electron transistor (SET). It's used in charge sensor applications, infrared radiation detectors, and spectroscopy. However, it faces limitations in lithography, co-tunneling effect, low gain, high output impedance, and background charges. Therefore, prior simulation is needed to optimize SET's work function and understanding physics concepts. A master equation approach is used to propose a new model …
Published in Journal of Semiconductor Devices and Circuits · Vol. 10, Issue 3, 2024 · pp. 19–25 Read article
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GSM based Multiuser E-Notice Board using Wireless Technology
Abstract: AbstractWireless technology is now taking over the entire world. It has helped in shrinking the world. GSM technology is the most popular wireless technology which is now fastest growing technology in the electronic industry. Advancement in technology has brought about digitization to the core. Even the billing system, attendance system, health monitoring, etc., have all got digitized and so are the advertisement boards and the announcement boards. The existing system …
Published in Journal of Communication Engineering & Systems · Vol. 4, Issue 1, 2014 · pp. 13–20 Read article
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CMOS Gm-C IF Filter using SCA for Dual Band Receiver
Abstract: This paper deals with design of folded cascode OTA-C filter, which works for frequencies for RF application, based on transistor sizing methodology and simulation results are performed using SPICE software and BSIM3V3 model for CMOS 0.18 μm process, show that the designed folded cascode OTA has a 52 dB DC gain and provides a unit gain bandwidth of around 400 MHz. Design of CMOS Gm-C 2nd order Biquad filter implementation …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 3, 2015 · pp. 18–36 Read article
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Design and Analysis of Source Current Effect on Preamplifier-Positive Feedback-based CMOS Comparator Using 90 nm Technology
Abstract: One of the most important and essential components of the data converter circuit is the comparator and this paper presents the implementation and characterization of the basic and simplest CMOS comparator in 90 nm technology. Once the technology scales down, the design and implementation becomes an essential issue at sub-micron and deep-sub-micron technology. The behavior of the threshold voltage in the CMOS is not a linear quantity when the parameters …
Published in Journal of VLSI Design Tools and Technology · Vol. 3, Issue 3, 2013 Read article
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Design and Implementation of A 4-bit Multiplier using Wallace Tree Architecture in 180 nm Technology
Abstract: Over the period of last decade, power dissipation has become one of the most important factors for VLSI designers in the design of most digital systems. Even though the speed and area are considered to be the critical factors in design of digital systems, there is a trade of with power consumption. Adders and multipliers are the most important arithmetic units in a processor and the major sources of power …
Published in Journal of Microcontroller Engineering and Applications · Vol. 2, Issue 1, 2015 · pp. 17–23 Read article
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High Performance Multi-Valued Logic (MVL)Gate Design Using FinFET
Abstract: CMOS scaling faces challenges such as leakage, power dissipation, and short channel effects. Multi-Valued Logic (MVL) offers higher information density and reduced interconnections. This work presents a FinFET-based MVL gate design that improves electrostatic control, switching speed, and reliability. Simulation results confirm reduced leakage power and enhanced performance compared to conventional logic. The proposed architecture demonstrates scalability for advanced technology nodes. It also shows potential for low-power applications in portable …
Published in Journal of Microelectronics and Solid State Devices · Vol. 13, Issue 1, 2026 · pp. 34–45 Read article
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Design and Implementation of High-Speed Low Power Low Area Hybrid One Bit Full Adder Using CMOS Technology
Abstract: In this article, we'll take a look at a new kind of Full Adder (FA) design that mixes traditional Complementary Metal Oxide Semiconductors (CCMOS) with Pass Transistors (PTs) and Transmission Gates (TGs). To analyze the circuit's performance, we used the Mentor Graphics software package. Since all twenty (20) varieties of Full Adder circuits were able to be measured and compared, this research was conducted. When the clock rate of the …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 1, Issue 2, 2023 · pp. 29–39 Read article
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Design and Simulation of Low Power Allow Area High Speed Carry Save Adder using CMOS 16 nm Technology.
Abstract: In this article, we propose a novel 1-bit hybrid full adder circuit that is implemented using eighteen transistors. Simulations are done using the Mentor Graphics Tool 16nm technologies. The performances are evaluated based on their speed, average power consumption, and power-delay product. The essential components of arithmetic units including compressors, comparators, parity checkers, etc. are full adders. Thus, raising the performance of the entire adder will raise the system's performance. …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 1, Issue 2, 2023 · pp. 17–28 Read article
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A Novel Design for Power Reduction in Arithmetic Circuits using MTCMOS Technology
Abstract: In CMOS logic circuits, the reduction in the threshold voltage due to voltage scaling leads to increase in the subthreshold leakage current and hence static power dissipation. Although power consumption is important for modern VLSI design, operation speed and occupied area are still the main requirements of the VLSI design. Multi threshold voltage CMOS (MTCMOS) technology is a good solution which provides a high performance and low-power design without any …
Published in Journal of VLSI Design Tools and Technology · Vol. 4, Issue 1, 2014 · pp. 1–7 Read article
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Design and Simulation of Low-power, High-speed Effective Area Mux Based One-bit Full Adder Using CMOS Technology
Abstract: Our findings reveal a novel kind of circuit capable of performing both XOR and XNOR operations in parallel. Power dissipation and delay are both greatly reduced in the proposed circuits due to their low output capacitance as well as minimal short-circuit power dissipation. We show six new hybrid 1-bit full-adder (FA) circuits that take use of the XOR-XNOR or XOR/XNOR gates' special full-swing function. Each potential circuit layout has both …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 1, Issue 1, 2023 · pp. 25–33 Read article
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Design and Implementation of Low Power and Area Efficient Sub Threshold Level Shifter Using 16 nm CMOS Technology
Abstract: An efficient method of modifying subthreshold voltages is proposed here. As an alternative to static power dissipation, the suggested design allows for charging of internal nodes through VDDH. The force of the pull-down mechanism may be increased by connecting a second auxiliary circuit. The transition energy for input frequencies between 1 and 5 MHz is 84 fJ, the propagation delay is 46 ns, the dynamic power dissipation is 0.3 mW, …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 1, Issue 1, 2023 · pp. 16–24 Read article
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A study on CMOS Operational Amplifier in Sensor Development
Abstract: CMOS operational amplifiers (op-amps) have emerged as pivotal components in modern sensor development, enabling the amplification and conditioning of weak signals with high precision and efficiency. Their inherent advantages low power consumption, compact size, and seamless integration with digital circuits make them ideal for advancing miniaturized, battery-powered sensor systems in fields ranging from biomedical devices to IoT networks. By delivering precision, power efficiency, and integration, CMOS op-amps are not just …
Published in Journal of VLSI Design Tools and Technology · Vol. 16, Issue 1, 2026 · pp. 01–07 Read article
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Design and Implementation of 2nd Order Gm-C IF Tuning Filter Operating at 900 MHz and 88–108 MHz Wireless System for Multi Standard Receiver
Abstract: This paper deals with design and optimization of folded cascode OTA-C filter, which works for frequencies that lead to a base band circuit design for RF application, is based on transistor sizing methodology and Simulation results are performed using SPICE software and BSIM3V3 model for CMOS 0.18 μm process, show that the designed folded cascode OTA has a 52 dB DC gain and provides a Unit gain bandwidth of around …
Published in Journal of VLSI Design Tools and Technology · Vol. 4, Issue 1, 2014 · pp. 8–24 Read article
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A 32-Bit Booth Multiplier Design Using GDI Logic Style
Abstract: Gate diffusion input (GDI) is the newest technology of designing a low-power digital combinational circuit. This logic allows reducing power dissipation, delay and area of any digital logic circuit. The gate diffusion input logic allows implementation of a wide range of any complex logic function. These functions can be realized using only two transistors. This technique is preferred for designing fast using less number of transistors while improving logic level …
Published in Trends in Electrical Engineering · Vol. 5, Issue 3, 2015 · pp. 1–5 Read article
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GDI Logic Implementation of Variable Sized CSLA Architectures Using 45 nm SOI Technology
Abstract: Carry select adder (CSLA) is an efficient adder used in modern processors. But, the CMOS logic implementation at the transistor level makes it complex. The use of smaller transistor size has shrunk the overall design but the transistor count was retained. Hence, in this paper the transistor level implementation of variable sized CSLA architecture is done using gate diffusion input (GDI) logic. This implementation drastically simplifies the CSLA in terms …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 1, 2016 · pp. 78–88 Read article
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Implementation of 2nd Order CMOS Gm-C IF Tuning Filter Operating at GSM and FM Band: Wireless System with Monte Carlo Analysis
Abstract: Designed folded cascode OTA has a 52 dB DC gain and provides a unit gain bandwidth of around 400 MHz. Design of CMOS Gm-C 2nd order biquad filter implementation using OTA, operating at center frequency 70 and 10.6 MHz. The filter can be operated at center frequency of 70 MHz under 1.8 V power supply and is suitable for intermediate frequency (IF) range in most of the wireless systems operating …
Published in Journal of Electronic Design Technology · Vol. 5, Issue 2, 2014 · pp. 9–24 Read article
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Performance Analysis of CMOS and FinFET Based SRAM
Abstract: As CMOS devices are scaled to nanometer regime, the consequences such as short channel effects and variations in the process parameters are increased which affects the reliability and performance of the circuit. In order to over these issues, FinFET can be used as a suitable replacement for CMOS as it is a promising and better technology without sacrificing the reliability and performance of the applications and the circuit design. In …
Published in Journal of VLSI Design Tools and Technology · Vol. 8, Issue 3, 2018 · pp. 23–27 Read article
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Tuning Range, Phase Noise and Jitter Analysis of Current Starved Voltage Controlled Oscillator (VCO) for Digital PLL in 45 nm CMOS Technology
Abstract: A wide tuning range, low phase noise and low jitter 100 MHz Voltage-Controlled Oscillator (VCO) for DPLL was designed and implemented by 45 nm CMOS process technology using LT spice. There was a relation between the frequency tuning range, phase noise, and jitter at output of the VCO after linearizing the gain. Simulations using PTM 45 nm CMOS process technology shows, that a wide operation frequency range (tuning range) from …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 2, 2015 · pp. 81–89 Read article
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A High Performance Reference Circuit with Optimized Input Offset Operational Amplifier using Device Mismatch Model
Abstract: In this paper, author describes a band gap reference (BGR) circuit, having reference voltage 1.20V with maximum temperature coefficient of 63 ppm/0C in temperature range of –40 to 120 0C. The circuit operates in range of supply voltage, 3.0V to 3.6V. An operational amplifier (op-amp), whose input offset voltage is reduced upto 892 µV using Pelgrom’s device mismatch model is used in BGR. The power supply rejection ratio of circuit …
Published in Journal of VLSI Design Tools and Technology · Vol. 3, Issue 1, 2013 · pp. 1–7 Read article