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45 articles for “Arithmetic operation”
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Representation of Knowledge Involving Soft Fuzzy Numbers and Its Application in Decision Making Problems
Abstract: In this study, we introduce the concept of a soft fuzzy number and study its arithmetic operations, a fuzzy number valued measure and an aggregation operator on the collection of soft fuzzy numbers. In real life situations, the perception of characteristic feature of an entity or a collection of entities is expressed by us as soft fuzzy number valued information system, so that the loss of information in understanding the …
Published in Recent Trends in Parallel Computing · Vol. 6, Issue 1, 2019 · pp. 38–47 Read article
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Low-Power and Area-Efficient N-Bit Carry-Select Adder
Abstract: Design of High Efficiency Carry Select Adder Using SQRT Technique presents many opportunities for increasing the speed and reducing the area of any data processor. Only Carry Select Adder (CSLA) is the fastest adders which are used in many data-processing processors to perform fast arithmetic operation. From the structure of the CSLA, it is clear that there is scope for reducing the area and delay in the CSLA. In this …
Published in Journal Of Network security · Vol. 5, Issue 1, 2017 · pp. 22–27 Read article
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High Throughput RISC Processor Design Using Vedic Mathematics: A Review
Abstract: The load on general processor is increasing. It is of the utmost importance in the arithmetic unit for fast operations. Multipliers have a significant impact on how well the Arithmetic Unit performs. In this way, analysts are constantly looking for new methodologies and equipment to execute number juggling activity in tremendous proficient manner in the terms of speed and region. Vedic Science is the old arrangement of math which has …
Published in Research & Reviews: A Journal of Embedded System & Applications · Vol. 10, Issue 2, 2022 · pp. 29–33 Read article
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Proposed System: Quantum Computing Processor Based on Linear Number Relation
Abstract: This paper details the design and implementation of a specialized quantum processor tailored for efficiently evaluating custom mathematical formulas. Optimized to perform a specific set of arithmetic and logical operations, this processor delivers a stable and high-performance computing platform. Unlike general-purpose quantum processors, which are designed for versatility across a wide range of algorithms, this dedicated processor aims to enhance performance and accuracy for a targeted set of tasks. The …
Published in Recent Trends in Parallel Computing · Vol. 11, Issue 3, 2024 · pp. 24–32 Read article
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Half Adder Using Different Design Styles: A Review on Comparative Study
Abstract: AbstractA half adder is a digital logic circuit that performs addition of two single bit binary numbers. Generally, in various types of processors, adders are used to perform arithmetic and logical operations .In this paper, working of half adder is analysed by designing it by using three different logic styles, i.e., CMOS logic, Transmission Gate Logic (TGL) and Pass Transistor Logic (PTL). The comparison has been made between the circuits …
Published in Journal of Advancements in Robotics · Vol. 7, Issue 3, 2020 · pp. 26–32 Read article
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Design and Simulation of 4-bit Multiplier using Carry Look-Ahead Adder at Transistor Level
Abstract: Multiplication is a basic operation performed in the Arithmetic Logic Unit, Digital signal processing, Floating-point unit and Application specific integrated circuits. This paper deals with the design and simulation of the 4-bit multiplier using a carry look-ahead adder at the transistor level. The total design process involves hierarchical implementation. Where the basic gate operations like AND, OR, NOT, and XOR are repeatedly used for designing the entire circuit. So, the …
Published in Journal of VLSI Design Tools and Technology · Vol. 11, Issue 3, 2021 · pp. 10–18 Read article
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Study And Literature Analysis of The Coarse-Grained Logic Interface with Floating-Point Arithmetic Unit
Abstract: Field-Programmable Gate Arrays (FPGAs) have become an essential digital circuit implementation techni que. The research looks at the design parameters by evaluating the building of an arithmetic logic unit (ALU) in Xilinx Vivado utilizing Hardware Description Language (HDL) and implementing common Field Programmable gate arrays (FPGAs). The ALU is a logic design component in digital computers that seeks to deliver optimal algorithms to maximize the usage of available hardware. The …
Published in Journal of VLSI Design Tools and Technology · Vol. 13, Issue 2, 2023 · pp. 45–55 Read article
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On Graph Theory Based on Matrix
Abstract: This paper presents a new approach of graph theory based on natural numbers and matrix only. The natural number is used for vertex and matrix for the edge. The fast graph generation is an advantage of this approach by the successor function. The connected and non-connected graph both is defined by the axiom. There is the arithmetic based on the additive and multiplicative operation over the matrix with the set …
Published in Research & Reviews: Discrete Mathematical Structures · Vol. 9, Issue 1, 2022 · pp. 40–46 Read article
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Machine Learning–Guided Cognitive RF System with Dynamic FFT Resolution and Multiplier Reconfiguration for Adaptive Anti-Jamming Communication
Abstract: This paper presents a hierarchical adaptive RF communication system that integrates signal quality-based pre- processing with machine learning-driven signal classification to achieve robust and resource-efficient operation in dynamic, interference-prone environments. Unlike prior art that addresses adaptive RF, ML classification, or anti-jamming individually, this work uniquely combines real-time SNR/RSSI-based signal strength estimation with dynamic FFT size selection (64-, 256- , or 512-point) and arithmetic-level multiplier reconfiguration (CORDIC, Distributed Arithmetic, and hybrid …
Published in International Journal of Radio Frequency Innovations · Vol. 4, Issue 1, 2026 Read article
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Algebraic Foundations of AES (Advanced Encryption Standard): Group Theory and Finite Field Applications in Symmetric Cryptography
Abstract: This paper presents a mathematical study of symmetric cryptographic algorithms, with a particular emphasis on the Advanced Encryption Standard (AES), which is one of the most widely used encryption schemes in modern security applications. The study highlights how abstract mathematical frameworks such as group theory, finite fields, and vector space concepts provide the foundation for the design, implementation, and analysis of AES. By approaching the algorithm from a mathematical perspective, …
Published in Recent Trends in Mathematics · Vol. 2, Issue 1, 2025 · pp. 12–16 Read article
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Low-Power Reconfigurable Digital Filter Design Using FPGA for IoT Edge Devices
Abstract: The rapid evolution of the Internet of Things (IoT) has led to an exponential increase in the deployment of edge devices that continuously process real-time sensor data under strict power, latency, and computational constraints. Digital filtering remains a critical operation in these devices, supporting tasks such as noise removal, data conditioning, and feature extraction for intelligent decision-making. However, conventional filter implementations on microcontrollers or fixed digital signal processors often struggle …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 3, Issue 2, 2025 · pp. 23–34 Read article
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A Novel Design for Power Reduction in Arithmetic Circuits using MTCMOS Technology
Abstract: In CMOS logic circuits, the reduction in the threshold voltage due to voltage scaling leads to increase in the subthreshold leakage current and hence static power dissipation. Although power consumption is important for modern VLSI design, operation speed and occupied area are still the main requirements of the VLSI design. Multi threshold voltage CMOS (MTCMOS) technology is a good solution which provides a high performance and low-power design without any …
Published in Journal of VLSI Design Tools and Technology · Vol. 4, Issue 1, 2014 · pp. 1–7 Read article
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Modelling and Electrical Characterization of Single Electron Transistor
Abstract: A nano-electronic device with low power consumption, high performance, and quantum effects is the single electron transistor (SET). It's used in charge sensor applications, infrared radiation detectors, and spectroscopy. However, it faces limitations in lithography, co-tunneling effect, low gain, high output impedance, and background charges. Therefore, prior simulation is needed to optimize SET's work function and understanding physics concepts. A master equation approach is used to propose a new model …
Published in Journal of Semiconductor Devices and Circuits · Vol. 10, Issue 3, 2024 · pp. 19–25 Read article
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Design And Optimization Of High-Speed Array Multiplier
Abstract: An array multiplier is a digital circuit used for the rapid multiplication of binary numbers. It employs an array of logic gates to generate partial products concurrently, significantly enhancing speed. The array structure divides the multiplication task into smaller, parallel processes, allowing for efficient parallel processing of multiple bits. Each cell within the array manages specific bit-level multiplications, and their results are summed to produce the final product. This parallel …
Published in Journal of Microelectronics and Solid State Devices · Vol. 11, Issue 3, 2024 Read article
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Spintronic Logic Circuits for Ultrafast Processing
Abstract: Spintronic logic has emerged as one of the most promising post-CMOS paradigms capable of addressing the speed, density, and energy challenges of deeply scaled silicon technologies. By relying on the intrinsic properties of electron spin and magnetization dynamics, spintronic devices—particularly Magnetic Tunnel Junctions (MTJs), Spin-Transfer Torque (STT), and Spin–Orbit Torque (SOT) structures—enable ultrafast, non-volatile data processing with significantly reduced energy consumption. Despite remarkable device-level advancements, circuit- level realization of high-speed, …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 3, Issue 2, 2025 · pp. 35–43 Read article
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A Novel Design for High Speed & Area Efficient Compressor Based Vedic Multiplier
Abstract: Multipliers are the most important part in any arithmetic and logic unit, AbstractMultipliers are the most important part in any arithmetic and logic unit, accumulators and digital signal processors. Due to the increasing constraints on delay, the design of faster multipliers is emphasized. Among several multipliers, Vedic multipliers are preferred for their speed of operation. Here the proposed Vedic multiplication techniques are based on “URDHVA TIRYAKBHYAM” a fast and efficient …
Published in Journal of Microelectronics and Solid State Devices · Vol. 5, Issue 3, 2018 · pp. 1–10 Read article
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Optimized Hardware Realization of AES for High-Throughput FPGA Platforms
Abstract: The Advanced Encryption Standard (AES) is the predominant symmetric-key cryptographic algorithm used for securing digital communication across embedded systems, IoT devices, cloud infrastructures, and defense networks. Although software-based AES implementations offer flexibility, they often fail to meet the high-speed, low-latency, and energy-efficient requirements of modern real-time applications. Reconfigurable hardware platforms such as Field-Programmable Gate Arrays (FPGAs) provide a powerful alternative by enabling architectural customization, intrinsic parallelism, and optimized hardware acceleration. …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 3, Issue 2, 2025 · pp. 11–22 Read article
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Design and Validation of Low Power High Speed area effective comparator using CMOS Technology
Abstract: The most fundamental arithmetic comparisons in a digital comparator involve comparing two numbers that are greater than, less than, or equal to each other. While doing enormous level arithmetic comparisons, a digital comparator needs more space, which results in higher power consumption and a delayed response. This can be solved by using N-bit comparator with two modules using 45GPDK CMOS Technology. An N-bit comparator can operate at extremely high speeds …
Published in Recent Trends in Electronics Communication Systems · Vol. 10, Issue 2, 2023 · pp. 20–29 Read article
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Comparative Study of a 32 bit Clock Gated ALU based on Carry Skip Adder and Ripple Carry Adder
Abstract: The ALU is one of the most frequently accessed modules in a CPU and is utilized during most instruction executions. Hence the power consumption of the ALU is a major concern. In this paper a low power 32 bit ALU is designed using VHDL. Lower power consumption is achieved by using clock gating technique than conventional design. A carry skip adder with variable block length is used for the arithmetic …
Published in Journal of VLSI Design Tools and Technology · Vol. 3, Issue 2, 2013 · pp. 6–11 Read article
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Comparative Study of Psychomotor Performance in Depression Patients with Healthy Volunteers
Abstract: Antidepressant drug therapy can affect psychomotor performance of patients suffering from depression. Hence, the present study was planned to assess the psychomotor performance of under therapy depression patients with healthy volunteers using battery of psychometric tests. Twenty under therapy patients suffering from depression and taking antidepressant drugs treatment for not less than six months were compared with 20 healthy volunteers. The psychometric test battery included three subjective visual analogue scales …
Published in Research and Reviews : A Journal of Medical Science and Technology · Vol. 2, Issue 1, 2013 · pp. 15–18 Read article