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70 articles for “Adders”
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1-Bit Full Adder's Analysis and Comparison
Abstract: The full adder circuit forms the basis of majority of digital circuits. Improvement in a basic full adder circuit in terms of area, power and delay affect the performance of whole system. It becomes compulsory to investigate and analyze the performance of implementation of full adder circuit in literature, till now. In this paper, a study is carried out to look into performance parameters of full adder circuit using different …
Published in Journal of Electronic Design Technology · Vol. 6, Issue 2, 2015 · pp. 1–6 Read article
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Implementation of Carry Select Adder with Reduced Area Scheme
Abstract: Addition is the heart of arithmetic unit and the arithmetic unit is often the work horse of a computational circuit. So, adders play a key role in designing an arithmetic unit and also many digital integrated circuits. Carry select adder (CSLA) is one of the fastest adders used in many data processors and in digital circuits to perform arithmetic operations. But CSLA is area-consuming because it consists of dual ripple …
Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 1, 2017 · pp. 1–5 Read article
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Comparative Analysis of CMOS CNFET and Memristor Based Full Adder Circuits and CMOS Memristor Based Multiplexer Circuits
Abstract: Continued developments in microelectronics technology have led to a myriad of new compute-intensive applications at the micro-edge, such as artificial intelligence and signal and image processing. Multiplication is a crucial arithmetic process in such applications. However, large logic complexities typically seen in traditional multipliers generate combinatorial blocks with long chains of cascaded carry addition. As such, energy efficiency has remained a primary design challenge for these applications, when powered by …
Published in Journal of VLSI Design Tools and Technology · Vol. 12, Issue 2, 2022 · pp. 22–33 Read article
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Low-power, High-speed, Full-swing Hybrid Full Adder
Abstract: Abstract: Nowadays VLSI design demands low area and low-power consumption. In this study, a low-power, high-speed, full-swing 1-bit hybrid full adder is proposed. The hybrid full adder is decomposed into three sub-modules. For each sub-module, designs are different. Module 1 and 2 are designed using pass transistor logic (PTL) and Module 3 uses transmission gates to produce carry signal. Then by proposed low-power, high-speed hybrid full adder circuits play a …
Published in Research & Reviews: A Journal of Embedded System & Applications · Vol. 7, Issue 3, 2019 · pp. 22–29 Read article
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Simulation of Adder Circuit Using Reversible Gates in Verilog HDL
Abstract: The emerging field of quantum computing uses quantum logic gates. The reversibility of logic gates is an important aspect of quantum logic gates used in VLSI and quantum computing. Reversibility ensures that power consumption is minimized. This study explores the field of reversible logic and utilizes Peres gate to develop a full adder circuit that shows a significant reduction in power consumption in simulations performed in Xilinx Vivado. We have …
Published in Journal of VLSI Design Tools and Technology · Vol. 14, Issue 3, 2024 · pp. 32–38 Read article
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Performance Analysis of 1-Bit Full Adder using GDI and CMOS Logic
Abstract: The adder is one of the most essential part in math processor, multiplier, and in various scientific applications. Full adder plays important role in multiplier architecture. In this paper a 1-bit full adder using GDI and CMOS logic has been implemented and comparative analysis has been done. The less delay and low power consumption is achieved for this implementation. This paper presents comparison of number of transistors have been used …
Published in Journal of Electronic Design Technology · Vol. 6, Issue 2, 2015 · pp. 18–22 Read article
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Different Compressor Adders
Abstract: AbstractMultipliers are one of the main blocks which decide the circuit performance as well as computation speed. In multiplication, addition of partial products contributes most to the circuit delay, power, and area. In this project, compressor adders are used to reduce this delay. Hence, compressors are a major part of the multiplier circuit that decides the overall speed of the system. For high-speed processing and higher systems, a huge number …
Published in Journal of Semiconductor Devices and Circuits · Vol. 5, Issue 2, 2018 · pp. 19–26 Read article
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A Unified Ultra-Low Power Architecture of Probabilistic Adder Based on GDI Technique
Abstract: In the present arena of technology scaling, the power consumption in the deep submicron technology plays a pivotal role as the transistor counts increases dramatically. Therefore, the need of the hour is to focus on power dissipation. The rate of occurrences of errors in the present VLSI scenarios has become higher and inevitable, and is increasing along with technology scaling. Eradicating all the errors is a cumbersome task; still a …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 3, 2016 · pp. 45–55 Read article
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Comparative Analysis of Partial Product Addition in Vedic Urdhva Tiryakbhyam Multiplier
Abstract: Multiplication is one of important operations performed in many digital signal processing applications. Hence the performance of the multiplier will affect the overall performance of the DSP processor. The methods like booth multiplier, and array multiplier are used. Vedic multiplication technique had proved its importance in getting the speed of multiplication. It is required to add the generated partial products quickly, to generate the result of multiplication faster. To add …
Published in Journal of VLSI Design Tools and Technology · Vol. 13, Issue 1, 2023 · pp. 15–32 Read article
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Performance Analysis of 1-Bit Half Adder using Different Combinational MOS Logics
Abstract: AbstractAdder is required for many processors designing like microprocessors, digital signal processors, image processing and various VLSI applications. The overall performance of system depends upon the adder circuits due to its presence mainly in critical paths of system. This paper presents half adder circuits using different combinational MOS logics. All the circuits were analyzed to find the most suitable circuit which consumes less power without costing the speed of the …
Published in Journal of Microelectronics and Solid State Devices · Vol. 4, Issue 3, 2017 · pp. 19–27 Read article
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Implementation of FIR Filter with Reverse Converter based RNS Kogge–Stone Adder
Abstract: AbstractLow power very large scale integration (VLSI) circuits are pertinent for designing of steep overall performance and adjustable devices. In current technology VLSI plays a vital role to reduce power consumption and delay. In analog to digital converter process, adder plays a crucial role. The authority of nonviolent issue is increasing regularly because of changing that a way, packaging and cooling cost, transportable route of motion and reliability. This freebie …
Published in Journal of Microelectronics and Solid State Devices · Vol. 5, Issue 2, 2018 · pp. 34–43 Read article
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Design and Performance Analysis of Full Adder Cell using FinFET Technique at 32nm Technology
Abstract: AbstractIn this paper, discussed is the comparative analysis of complementary MOS (CMOS) and dual gate-FinFET (fin shaped field effect transistor) based full adder cell design. To reduce the average power, average current and maximum current of 1-bit full adder circuit a new high DG-FinFET technique is presented. Use of double-gate FinFET technology provides low leakage and high performance operation. For MOSFET transistor model, a predictive technology model (PTM) BSIM4 and …
Published in Journal of Microelectronics and Solid State Devices · Vol. 4, Issue 3, 2017 · pp. 1–8 Read article
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Which is the Best 10T Static CMOS Full Adder for Ultralow-Power Applications?
Abstract: This paper presents the analysis of various 10-transistor CMOS 1-bit full adder circuits in terms of their output levels and finds out the suitable adder cell at 200 mV in subthreshold region at 16-nm technology node for ultra-low power applications. This paper also provides worst case output levels (sum and carry) of all the analyzed adder cells (which are presented in the paper) for various input combinations.Keywords: CMOS, carry, 2:1 …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 1, 2015 · pp. 45–50 Read article
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Review of Design and Implementation of Adder with Increasing Bits by Using Constant Delay Logic Style
Abstract: A different logic style including the constant logic style is proposed in this paper which is helpful in increasing the high speed applications. It is suitable for implementing the complicated arithmetic expressions. The objective of this paper is to reduce the delay, noised margin and power consumption. The transistor for minimal power delay product and energy delay product is proposed in this paper. The design and implementation of adder in …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 2, 2015 · pp. 38–41 Read article
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A New High Speed Low Power 1 Bit Full Adder
Abstract: This paper proposes a low power, low area and high speed 1-bit full adder compared to earlier 1bit full adder designs. The adder comprises of eight transistors with some modifications over the other existing design, so that it can invariably be used in the device with least nano device dimensions. The proposed design exhibits lower threshold loss and works faithfully in sub-threshold regime with appreciable voltage swing at lower power …
Published in Journal of VLSI Design Tools and Technology · Vol. 3, Issue 1, 2013 · pp. 8–13 Read article
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Design of High-Speed and Low-Power Carry Skip Adder
Abstract: In this brief, we present a high speed and lower power consumption carry skip adder (CSKA) architecture compared with the conventional one. The increment of speed is attained by implementing concatenation and incrementation strategy to improve the efficiency of the conventional CSKA (Conv-CSKA) architecture. Instead of make use of multiplexer logic, the proposed architecture makes use of AND-OR-Invert (AOI) and OR-AND-Invert (OAI) combination gates for the carry skip logic. The …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 3, 2016 · pp. 35–44 Read article
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Design and Implementation of High-Speed Low Power Low Area Hybrid One Bit Full Adder Using CMOS Technology
Abstract: In this article, we'll take a look at a new kind of Full Adder (FA) design that mixes traditional Complementary Metal Oxide Semiconductors (CCMOS) with Pass Transistors (PTs) and Transmission Gates (TGs). To analyze the circuit's performance, we used the Mentor Graphics software package. Since all twenty (20) varieties of Full Adder circuits were able to be measured and compared, this research was conducted. When the clock rate of the …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 1, Issue 2, 2023 · pp. 29–39 Read article
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Design of Optimized Full Adder using Noise-Mitigation Techniques and Power Gating
Abstract: With the advent of nanoscale technology, a new era of power consumption, speed, and reliability challenges for traditional static CMOS logic has begun. To solve these problems, dynamic logic families—particularly domino logic—have emerged as potent substitutes that offer quicker processing speeds and lower power consumption. The design and optimization of a full adder circuit using domino logic is shown in this study. A dynamic domino logic technique is used to …
Published in Journal of Microelectronics and Solid State Devices · Vol. 11, Issue 3, 2024 · pp. 1–6 Read article
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An Efficient RNS Based Sparse Kogge Stone Parallel Pre-fix Adder with Filter
Abstract: AbstractLow power very large-scale integration (VLSI) circuits are important for designing of high performance and portable devices. Along with that the high speed, small area and low cost are also the main considerations of VLSI circuits. The importance of low power is increasing day by day because of changing trend, packaging and cooling cost, portable system and reliability. This paper presents the design of Digital FIR filter using reverse converter …
Published in Journal of Semiconductor Devices and Circuits · Vol. 5, Issue 1, 2018 · pp. 43–51 Read article
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Hardware and Power Efficient Single Bit Full Adder Using GDI and PTL Technique
Abstract: Abstract: This study presents hardware and power efficient single bit full adder which consists of two techniques, Pass Transistor Logic (PTL) and Gate Diffusion Technique (GDI). Several logic families are described by PTL which is utilized in the architecture of integrated circuits. PTL technique is used to decrease the number of transistors in the circuits to make different logic gates. GDI technique is utilized for the low power consumption. CADENCE …
Published in Research & Reviews: A Journal of Embedded System & Applications · Vol. 7, Issue 3, 2019 · pp. 9–17 Read article