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357 articles for “low-power”
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Design and Implementation of High-Speed Low Power Low Area Hybrid One Bit Full Adder Using CMOS Technology
Abstract: In this article, we'll take a look at a new kind of Full Adder (FA) design that mixes traditional Complementary Metal Oxide Semiconductors (CCMOS) with Pass Transistors (PTs) and Transmission Gates (TGs). To analyze the circuit's performance, we used the Mentor Graphics software package. Since all twenty (20) varieties of Full Adder circuits were able to be measured and compared, this research was conducted. When the clock rate of the …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 1, Issue 2, 2023 · pp. 29–39 Read article
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A Comprehensive Review of CMOS Analog Circuit Design Techniques for Low-Power VLSI Systems
Abstract: CMOS analog circuit design plays a significant role in the development of modern low-power Very Large-Scale Integration (VLSI) systems used in wireless communication, biomedical devices, portable electronics, embedded systems, and Internet of Things (IoT) applications. Research on low-power CMOS analogue design methodologies has intensified because to the growing need for high-performance, small, and energy-efficient electronic products. However, reducing power consumption while maintaining signal accuracy, noise performance, stability, bandwidth, and overall …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 4, Issue 1, 2026 Read article
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A Neuromorphic-Inspired, Low-Power VLSI Architecture for Edge AI in IoT Sensor Nodes
Abstract: As the proliferation of Internet of Things (IoT) devices continues to rise, there is an increasing demand for real-time, energy-efficient artificial intelligence (AI) processing directly at the network edge. Traditional edge AI accelerators, often based on deep learning models like convolutional neural networks (CNNs), struggle to meet the ultra-low-power requirements of battery-constrained IoT sensor nodes. In response to this challenge, this study introduces a neuromorphic-inspired, low-power very- large-scale integration (VLSI) …
Published in Journal of Microelectronics and Solid State Devices · Vol. 12, Issue 2, 2025 · pp. 41–47 Read article
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Design And Implementation of Anti-Interference Low Power Double-Edge Trigger Flip-Flop Based On C-Element
Abstract: Double-Edge Triggered Flip-Flops (DETFFs) will use a lot more power when there are glitches and interference in the signal input. This work proposes an anti-interference low-power DETFF based on C-elements to efficiently lower the power consumption. This DETFF employs an enhanced C-element, which successfully filters input signal glitches, avoids redundant transitions within the DETFF, and lowers the transistor's charge and discharge frequencies. To lower its latency, the C-element has additionally …
Published in Journal of VLSI Design Tools and Technology · Vol. 15, Issue 1, 2025 · pp. 36–44 Read article
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Low-Power Reconfigurable Digital Filter Design Using FPGA for IoT Edge Devices
Abstract: The rapid evolution of the Internet of Things (IoT) has led to an exponential increase in the deployment of edge devices that continuously process real-time sensor data under strict power, latency, and computational constraints. Digital filtering remains a critical operation in these devices, supporting tasks such as noise removal, data conditioning, and feature extraction for intelligent decision-making. However, conventional filter implementations on microcontrollers or fixed digital signal processors often struggle …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 3, Issue 2, 2025 · pp. 23–34 Read article
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Design and Implementation of Low Noise Power Low and High Speed Three Stage Comparator Using 16nm Technology
Abstract: To meet the demands of quicker operation and reduced noise levels, this study proposes a new CMOS Three-based comparator version. Efficiency may be significantly improved by comparing the suggested model to existing ones. This is so because the suggested comparator would improve the efficiency of the current amplifier design. The suggested model drives the input pairs of the regenerator and the amplified stage, making for a quicker comparator. The structure …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 1, Issue 2, 2023 · pp. 10–16 Read article
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Development of Polymer Based SRAM Cell with Enhance Low Power Performance
Abstract: Low-power memory technologies are in high demand with the rapid growth of portable electronics and energy-efficient computing systems. Static random-access memory (SRAM) plays a crucial role in processors, cache memories, and system-on-chip applications due to their speed and reliability. Static Random Access Memory (SRAM) is typically implemented using complementary MOS (CMOS) technology, which integrates both PMOS (P-channel Metal–Oxide–Semiconductor) and NMOS (N-channel Metal–Oxide–Semiconductor) transistors. However, as technology scales to deep submicron …
Published in Journal of Polymer & Composites · Vol. 14, Issue 1, 2026 · pp. 1439–1448 Read article
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RTL-to-GDSII Flow Optimization for Low-Power 32-bit RISC-V Processor
Abstract: This paper presents the implementation and optimization of a 32-bit RISC-V processor, transitioning from Register Transfer Level (RTL) design to final GDSII using Synopsys Fusion Compiler over 32nm technology node. The processor architecture is based on the RV32I base instruction set and incorporates a 5-stage pipeline to achieve a balanced trade-off between performance and design complexity. The design methodology involved RTL synthesis, gate-level netlist generation, and successive physical design stages …
Published in Journal of VLSI Design Tools and Technology · Vol. 15, Issue 3, 2025 · pp. 1–10 Read article
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Design and Simulation of Low Power Allow Area High Speed Carry Save Adder using CMOS 16 nm Technology.
Abstract: In this article, we propose a novel 1-bit hybrid full adder circuit that is implemented using eighteen transistors. Simulations are done using the Mentor Graphics Tool 16nm technologies. The performances are evaluated based on their speed, average power consumption, and power-delay product. The essential components of arithmetic units including compressors, comparators, parity checkers, etc. are full adders. Thus, raising the performance of the entire adder will raise the system's performance. …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 1, Issue 2, 2023 · pp. 17–28 Read article
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Design and Implementation of Low-power SPI Shift Register
Abstract: SPI stands for serial peripheral interface which is used for serial, synchronous and full duplex communication of data between master and slave devices. Master devices can be Microprocessors or Microcontrollers; and slaves are the Peripheral devices interfaced with them. The main internal component for architecture of master/slave block is shift register which defines its operation. But as the size of the shift register increases, power is utilized to a greater …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 1, Issue 1, 2023 · pp. 1–15 Read article
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Design and Simulation of Low-power, High-speed Effective Area Mux Based One-bit Full Adder Using CMOS Technology
Abstract: Our findings reveal a novel kind of circuit capable of performing both XOR and XNOR operations in parallel. Power dissipation and delay are both greatly reduced in the proposed circuits due to their low output capacitance as well as minimal short-circuit power dissipation. We show six new hybrid 1-bit full-adder (FA) circuits that take use of the XOR-XNOR or XOR/XNOR gates' special full-swing function. Each potential circuit layout has both …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 1, Issue 1, 2023 · pp. 25–33 Read article
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DFT Compatible Low Power EDAC Based on Clock Gating
Abstract: The in-situ EDAC architecture is normally hired in timing-error tolerant circuits in a try and decrease the conservative timing protect band due to procedure, voltage, and temperature (PVT) fluctuations. But with the addition of the latch-based totally data channel, extra detection, and propagation common sense, it makes the implementation of the layout for- testability (DFT) tough. We present a new low area test overhead DFT EDAC architecture with extreme reduction …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 3, Issue 1, 2025 · pp. 41–53 Read article
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Developing low power consumption Solar Atmospheric water generator for dealing with water crisis
Abstract: Nowadays in India as well as in some places in the world there is a shortage of water. In the world, 46% of the population, which is nearly 2 billion people are unable to have a clean water source for a drink. This became a threat. On Earth, water is present in different forms. One of them is water vapor. The relative humidity on earth varies by season and place. …
Published in Journal of Nuclear Engineering & Technology · Vol. 14, Issue 3, 2024 · pp. 29–36 Read article
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Design and Implementation of Low Power and Area Efficient Sub Threshold Level Shifter Using 16 nm CMOS Technology
Abstract: An efficient method of modifying subthreshold voltages is proposed here. As an alternative to static power dissipation, the suggested design allows for charging of internal nodes through VDDH. The force of the pull-down mechanism may be increased by connecting a second auxiliary circuit. The transition energy for input frequencies between 1 and 5 MHz is 84 fJ, the propagation delay is 46 ns, the dynamic power dissipation is 0.3 mW, …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 1, Issue 1, 2023 · pp. 16–24 Read article
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Polymer Composite Nodes for Smart IoT Environmental Monitoring: Applying ML-Calibrated RF Sensors for Exceptionally Low-Power, Flexible, and Dependable Performance
Abstract: The quick usage of the Internet of Things (IoT) for monitoring the environment needs sensor platforms that are accurate, responsive, adaptable, energy-efficient, and able to work in many different conditions. This work presents polymer composite nodes equipped with machine learning (ML)-calibrated radio-frequency (RF) sensors that adhere to stringent criteria. Sensor substrates built of flexible polymer matrices with conductive fillers are strong, light, and flexible enough to fit on surfaces that …
Published in Journal of Polymer & Composites · Vol. 14, Issue 1, 2026 · pp. 1205–1221 Read article
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Design and Analysis of Low-Power CMOS Inverter Chains for High-Speed Digital Circuits
Abstract: This report briefly explains the design process, structure, and evaluation of a CMOS inverter designed using a 45 nm technology process with a focus on its propagation delay and power consumption. Moreover, the CMOS inverter design will be created using the Cadence Virtuoso design environment, along with a post-layout analysis of the design. Performance evaluation of the designed circuit will be carried out through the execution of a transient analysis …
Published in Journal of VLSI Design Tools and Technology · Vol. 16, Issue 1, 2026 · pp. 40–57 Read article
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Graphene–Perovskite Hybrid Opto-Electronic Modulators for Ultra-Low Power Optical Communication
Abstract: This paper proposes a novel self-adaptive neuromorphic opto-electronic transceiver architecture designed to enhance the intelligence, adaptability, and efficiency of next-generation optical communication networks. The proposed system integrates neuromorphic computing principles with photonic signal processing to enable real-time learning, dynamic resource allocation, and autonomous compensation of channel impairments such as dispersion, nonlinearities, and noise. Unlike conventional transceivers, the developed model employs spiking neural networks embedded within opto-electronic circuits to mimic biological …
Published in Trends in Opto-electro & Optical Communication · Vol. 16, Issue 1, 2026 · pp. 41–52 Read article
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Study of Energy Efficiency in IoT Devices
Abstract: The Internet of Things (IoT) is transforming industries and daily life by connecting billions of devices, yet its growth presents significant energy efficiency challenges. This paper explores strategies to address these challenges by investigating energy harvesting techniques and low-power communication protocols. Energy harvesting methods, including solar, kinetic, and thermal energy, offer sustainable alternatives to traditional battery-powered IoT devices, reducing dependency on non-renewable resources and enabling longer operational lifetimes. Simultaneously, low-power …
Published in Journal of Remote Sensing & GIS · Vol. 16, Issue 2, 2025 · pp. 34–40 Read article
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Current Controlled Oscillator Using FinFET
Abstract: A current-controlled oscillator using 18 nm FinFET technology is proposed in this study which consists of a Current Controlled Differential Difference Current Conveyor (CCDDCC) block to control the current. FinFET technology has better scalability and lower leakage current compared to traditional CMOS, which allows it to surpass the obstacles faced by CMOS-based oscillators. The suggested oscillator is suitable for electronic applications such as Phase-Locked Loop (PLL) systems, radio frequency (RF) …
Published in Journal of Semiconductor Devices and Circuits · Vol. 12, Issue 3, 2025 · pp. 17–28 Read article
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Neuromorphic Spiking Neural Networks and Event-Driven Hardware: Architectures, Learning Paradigms, and Experimental Realizations
Abstract: With the current computational boom the research community is seeking for more sustainable energy efficient i.e. biologically inspired models of conventional Artificial Neural Networks (ANNs). Spiking Neural Networks (SNNs) known as the third generation of neural network models, provide a revolutionary approach by mimicking the asynchronized event-driven and temporally accurate signaling of the mammalian brain. Whereas conventional deep learning models operate with real-valued activations and dense matrix multiplications, SNNs use …
Published in Current Trends in Signal Processing · Vol. 16, Issue 2, 2026 Read article