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91 articles for “VLSI circuits”
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A Circuit Approach for CMOS VLSI Circuit Leakage Power Reduction
Abstract: Despite the fact that scaling CMOS technology boosted speed, leakage currents always remained an issue. The issue has gotten worse as the scaling has gone into the UDSM (ultra-deep-submicron) range. In order for the circuit to function effectively, these unwanted leakage currents must be reduced to a minimum. It is challenging to create these leakage-free nano-scale CMOS circuits. In this work, the issue of leakage power is addressed, which occurs …
Published in Research & Reviews: A Journal of Embedded System & Applications · Vol. 10, Issue 3, 2022 · pp. 7–18 Read article
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Power Estimation for VLSI Circuits Using Neural Networks
Abstract: Neural network based VLSI power estimation is done which estimates power in VLSI circuits from its input/output and gate information, without simulation and analysis of its detail structure and the interconnections.Artificial neural network is created which helps in estimation of power. Power estimation results from the [2] [3]are used as the training vector for the network .The network is trained using Back-propagation algorithm. Asimple recurrent network is also introduced called …
Published in Journal of VLSI Design Tools and Technology · Vol. 1, Issue 1-2-3, 2011 · pp. 45–56 Read article
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Analysis of VLSI Circuits Designed with Single and Dual Channel Strained Silicon MOSFETs in Nanoregime
Abstract: In this paper, performance of the VLSI circuits designed with strained silicon MOSFETs is analysed andcompared with bulk MOSFET. Emphasis is being given on the evaluation of speed, power and noisecharacteristics. An inverter circuit designed with single channel and dual channel biaxial strained MOSFETsof 40 nm channel length and 0.3 germanium mole-fraction is being taken to evaluate the performance throughsimulation. The device design and circuit simulation is done in Sentaurus …
Published in Journal of VLSI Design Tools and Technology · Vol. 1, Issue 1-2-3, 2011 · pp. 15–20 Read article
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Optimizing Routing and Placement of VLSI Circuits with Differential Algorithms and Neural Networks
Abstract: The performance of modern VLSI systems is heavily influenced by power constraints, necessitating precise power estimation and effective optimization techniques. Traditional methods, such as gate-level simulations, are often slow and computationally intensive. This paper introduces DRPENN (Differential Algorithm for Routing and Placement Optimization using Neural Networks), an innovative solution that combines a Switching Activity Estimator (SAE) with a neural network-assisted differential algorithm. By leveraging toggle rates from simulations to train …
Published in Journal of VLSI Design Tools and Technology · Vol. 14, Issue 2, 2024 · pp. 14–20 Read article
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Comparative Analysis of MOSFET, CNTFET and NWFET for High Performance VLSI Circuit Design: A Review
Abstract: Nanowires are inimitable materials for considering phenomenon in nanoscale regime. Nanowires development exhibits ample of applications by controlling their, structure, composition as well as their electrical properties. This paper review diverse types of nanowires, nanowire field-effect transistor (NWFET) structure and their comparison with novel devices. Firstly, this paper describes different types of nanowires and nanowire heterostructure that shows nanowire heterostructures eliminates various factors that limit the performance of homogeneous nanowire …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 2, 2016 · pp. 19–32 Read article
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Analysis and Characterization of Circuits for Leakage Power Reduction at Sub-50 nm in CMOS Circuits
Abstract: This paper analyzes various techniques to decrease leakage power in complementary metal oxide semiconductor (CMOS) very large scale integration (VLSI) circuits, because due to continuous scaling of CMOS technology there is improvement in speed of semiconductor devices and the side effect of this scaling is leakage power. With the development of technology in CMOS VLSI Circuit, length of transistors has been reduced and speed of operation is increasing simultaneously. As …
Published in Journal of Electronic Design Technology · Vol. 13, Issue 2, 2022 · pp. 11–22 Read article
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Design of Decoder Using Domino Logic Circuit for VLSI
Abstract: Dissipation of power from a circuit is the major issue in the design of any VLSI circuit, which decreases the life span of a device/system. NMOS and PMOS circuits are very slow while switching the state from low to high. The speed of the circuit can be increased by decreasing resistance. This process in turn increases the static power dissipation. So, because of these disadvantages, CMOS circuits are used in …
Published in Journal of VLSI Design Tools and Technology Read article
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Design of Decoder Using Domino Logic Circuit for VLSI
Abstract: Dissipation of power from a circuit is the major issue in the design of any VLSI circuit, which decreases the life span of a device/system. NMOS and PMOS circuits are very slow while switching the state from low to high. The speed of the circuit can be increased by decreasing resistance. This process in turn increases the static power dissipation. So, because of these disadvantages, CMOS circuits are used in …
Published in Journal of VLSI Design Tools and Technology · Vol. 11, Issue 3, 2021 · pp. 42–54 Read article
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Delay Analysis for VLSI Interconnect’s Circuits
Abstract: This research work has been comprised of three parts. The first part deals with the implementation and estimation for the delay of an inverter and study of the influence of the delay variations with the increased size of the inverter. In this modern era of VLSI integrated circuits, interconnect’s delay majorly influences the device delay. The second phase of the work emphasizes on the realization of the interconnect delay and …
Published in Journal of Electronic Design Technology · Vol. 6, Issue 3, 2015 · pp. 25–32 Read article
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A Comprehensive Review of CMOS Analog Circuit Design Techniques for Low-Power VLSI Systems
Abstract: CMOS analog circuit design plays a significant role in the development of modern low-power Very Large-Scale Integration (VLSI) systems used in wireless communication, biomedical devices, portable electronics, embedded systems, and Internet of Things (IoT) applications. Research on low-power CMOS analogue design methodologies has intensified because to the growing need for high-performance, small, and energy-efficient electronic products. However, reducing power consumption while maintaining signal accuracy, noise performance, stability, bandwidth, and overall …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 4, Issue 1, 2026 Read article
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An Efficient RNS Based Sparse Kogge Stone Parallel Pre-fix Adder with Filter
Abstract: AbstractLow power very large-scale integration (VLSI) circuits are important for designing of high performance and portable devices. Along with that the high speed, small area and low cost are also the main considerations of VLSI circuits. The importance of low power is increasing day by day because of changing trend, packaging and cooling cost, portable system and reliability. This paper presents the design of Digital FIR filter using reverse converter …
Published in Journal of Semiconductor Devices and Circuits · Vol. 5, Issue 1, 2018 · pp. 43–51 Read article
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Cluster Based Sleep Transistor Approach for Low Power 6T SRAM Cell
Abstract: The demand of high density VLSI circuits has been increasing as the size of ICs is becoming small day by day. It has been seen that, to reduce active power dissipation in memory, the supply voltage reduction is necessary. Lowering the supply voltage is one of the most straightforward and effective ways to suppress the energy consumption because reducing the supply voltage could reduce the dynamic power and leakage power …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 1, 2016 · pp. 41–48 Read article
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Performance Comparison of Noise-Tolerant, High- Performance CMOS Domino Logic Configurations
Abstract: In high-performance VLSI chip design, domino logic configuration is often preferred over static logic due to its faster operation and smaller area footprint, especially in deep submicron (DSM) technology. However, DSM noise has become a significant challenge in domino-based circuits, leading to compromises in the reliability and signal integrity of integrated circuits (ICs). The switching threshold of domino logic, defined as the input voltage level at which the gate output …
Published in Journal of Semiconductor Devices and Circuits · Vol. 12, Issue 2, 2025 · pp. 35–50 Read article
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Implementation of Adders Using Ternary Based Multiple Valued Logic
Abstract: In today’s world VLSI chips are widely used in various branches of Engineering like Voice and Data communication networks, Digital signal processing, Computers, Commercial Electronics, Automobiles, Medicine and many more. So, there have been major advances in IC technology which have both made feasible and generated great interest in electronic circuits which employ more than two discrete levels of signals such circuits called Multiple valued logic circuits, offer several potential …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 1, Issue 2, 2023 · pp. 1–8 Read article
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A Survey on the various Adibatic Logic Styles used for Circuit Design in IOT & WSN Applications
Abstract: Abstract— This paper describes about different adiabatic logics are used which are all used to provide low power and high speed. Low power circuits and designs are the need of the hour as they find applications in electronic components which have power efficient processing capabilities. For IOT based applications we need to design low power VLSI circuits that utilize adiabatic logic in order to enhance the security and reduce the …
Published in Journal of Microcontroller Engineering and Applications · Vol. 9, Issue 2, 2022 · pp. 1–5 Read article
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A Survey on Recent Approaches for Leakage Power Reduction in MOS Integrated Circuits
Abstract: Today the integrated circuit’s functionalities are increasing day by day with increase in the number of transistors in it. However, the scaling of the transistors, top increase its number, for the same area of an IC reduces its sub-threshold voltage with its increase in the leakage power consumption. Scaling at different scales (45, 60, 90 nm, etc.) leads to major losses, both at static and dynamic phases of the circuits. …
Published in Journal of VLSI Design Tools and Technology · Vol. 4, Issue 2, 2014 · pp. 24–31 Read article
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Power Reduction at 90 nm through Circuit Level Modification
Abstract: Along with dynamic power, leakage power has turned out to be a major contributor to the overall power consumption in VLSI circuits. This problem is even more stringent in nano-scale dimension devices according to the International Technology Roadmap for Semiconductors (ITRS). As the technological advancements demand more function per device with a significant shrinking in device dimension, heat per unit area is also escalating at an elevated rate. This turns …
Published in Journal of VLSI Design Tools and Technology · Vol. 2, Issue 1-2-3, 2012 · pp. 101–107 Read article
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Implementation of FIR Filter with Reverse Converter based RNS Kogge–Stone Adder
Abstract: AbstractLow power very large scale integration (VLSI) circuits are pertinent for designing of steep overall performance and adjustable devices. In current technology VLSI plays a vital role to reduce power consumption and delay. In analog to digital converter process, adder plays a crucial role. The authority of nonviolent issue is increasing regularly because of changing that a way, packaging and cooling cost, transportable route of motion and reliability. This freebie …
Published in Journal of Microelectronics and Solid State Devices · Vol. 5, Issue 2, 2018 · pp. 34–43 Read article
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A Cuckoo Search based Approach for Solving Standard Cell Placement Problem
Abstract: The standard cell placement (SCP) is an NP complete problem in VLSI layout which focuses on placing the cells at appropriate locations so as to minimize the resultant wirelength. The standard cell placement is one of the significant phases in VLSI circuit design. Many heuristic approaches have been developed in literature to solve this problem. The paper presents an efficient nature-inspired meta-heuristic algorithm for solving the standard cell placement problem …
Published in Journal of VLSI Design Tools and Technology · Vol. 4, Issue 2, 2014 · pp. 1–7 Read article
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Hybrid Quantum-Classical Reinforcement Learning Enabled Thermal-Aware Electronic Design Automation Framework for Energy-Efficient Next-Generation VLSI Systems Applications
Abstract: Modern Very Large-Scale Integration (VLSI) systems are becoming more complicated, which has increased need for sophisticated Electronic Design Automation (EDA) frameworks that can concurrently optimise thermal behaviour, power consumption, and performance. This study proposes a Hybrid Quantum-Classical Reinforcement Learning (HQCRL) Enabled Thermal-Aware EDA Framework for next-generation energy- efficient VLSI systems. The proposed framework integrates quantum-inspired optimization techniques with classical reinforcement learning algorithms to address the challenges of placement, routing, and …
Published in Journal of Electronic Design Technology · Vol. 17, Issue 2, 2026 · pp. 10–22 Read article