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27 articles for “system on chip (SOC)”
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New trends in Radio Frequency design and making things smaller
Abstract: Recent improvements in wireless communication, the Internet of Things (IoT), and 5G/6G networks have made people want small, powerful radio frequency (RF) equipment. With an emphasis on how developments in materials engineering, circuit architecture, and packaging technologies are redefining RF system integration, this article offers a thorough evaluation of current developments in RF downsizing. System-on-Chip (SoC), System-in-Package (SiP), and Antenna-in-Package (AiP) ideas, which allow tightly integrated RF front-ends with enhanced …
Published in International Journal of Radio Frequency Innovations · Vol. 3, Issue 2, 2025 · pp. 28–34 Read article
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A Novel Architecture of Control System Processor Using Field Programmable Gate Array
Abstract: This paper presents a reconfigurable architecture of control system processor. The performance of the proposed architecture has been evaluated by taking different controllers and phase lead and phase lag networks. We designed the architecture of the processor and realizing the architecture using adder, multiplier, delay unit and validate it in the FPGA, which show that the hardware scheme is feasible for practical application. The experimental results clearly reveal the novelty …
Published in Journal of Microcontroller Engineering and Applications · Vol. 2, Issue 2, 2015 · pp. 13–20 Read article
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The Evolution of Digital Integrated Circuits: A Journey Through Technological Advancements
Abstract: The evolution of digital integrated circuits (ICs) is a remarkable journey that has transformed the worldof technology over the past several decades. This abstract provides an overview of the comprehensivearticle that explores this evolution. The journey begins with the birth of digital integrated circuits in thelate 1950s and early 1960s when the first ICs containing a small number of transistors emerged. Theseearly ICs laid the groundwork for a technological revolution …
Published in Journal of Microcontroller Engineering and Applications · Vol. 10, Issue 2, 2023 · pp. 15–18 Read article
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VHDL Implementation of Network-on-Chip Router using Round Robin Arbiter
Abstract: As the technology progresses, a large number of devices can be incorporated into a single chip. So, the communication between these devices becomes critical. The network-on-chip (NoC) is a technology used for such communication and overcomes the constraints of traditional bus-based system-on-chip (SoC). Router is the backbone of NoC and determines the performance to a great extent. This paper focuses on the implementation of five port virtual channel router which …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 3, 2016 · pp. 88–93 Read article
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A Physics-Informed Graph Neural Network Framework for Real- Time Thermal-Aware Fault Prediction and Adaptive Power Optimization in Heterogeneous System-on-Chip Architectures
Abstract: Heterogeneous System-on-Chip (SoC) architectures are increasingly adopted in edge computing, artificial intelligence, autonomous systems, and high-performance embedded platforms due to their superior computational efficiency and flexibility. However, increasing integration density and workload diversity introduce severe thermal hotspots, accelerated device degradation, and unexpected hardware faults that adversely affect system reliability and energy efficiency. This study proposes a Physics-Informed Graph Neural Network (PI-GNN) framework for real-time thermal- aware fault prediction and adaptive …
Published in Journal of VLSI Design Tools and Technology · Vol. 16, Issue 2, 2026 · pp. 19–28 Read article
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Test Time and Power Optimization of 2D SOCs Using GA and Greedy Algorithm
Abstract: This paper presents a genetic algorithm (GA) and greedy algorithm-based solution to co-optimize test scheduling under power constraint for core-based system-on-chips (SOCs). The core testing solutions are represented as set of wrapper configurations represented in rectangular bins of width equal to the test access mechanism (TAM) bandwidth and height equal to the corresponding test time. A best fit algorithm is used for the wrapper design. Experimental results are obtained for …
Published in Journal of Power Electronics and Power Systems · Vol. 5, Issue 2, 2015 · pp. 63–67 Read article
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Evaluation of Antenna Performance using a Novel Measurement Device: Methodology and Results
Abstract: In the last decade, the field of On Chip Antennas (OCA) has experienced unprecedented growth due to the introduction of small, low-cost, low-power System-on-Chip (SoC) wireless communication devices. OCAs are superior to conventional off-chip antennas in a number of ways. They first reduce the overall size of the wireless communication system since the presence of an OCA eliminates the need for an impedance matching network between the antenna and RF …
Published in Journal of Telecommunication, Switching Systems and Networks · Vol. 11, Issue 1, 2024 · pp. 24–29 Read article
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Survey of System-on-Chip Modular Test Approach
Abstract: The advancement in semiconductor technology over the past few decades has enabled the industry to develop new design and reuse methodologies referred as System-on-chip (SoC) design. These typically integrate heterogeneous mix of various complex analog and digital cores, with all their necessary electronic circuitry. The recent advancements have led to the use of the 3D structures (3D-SOCs) that brought along the benefits of higher performance, minimum average interconnect length, reduced …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 3, 2016 · pp. 56–70 Read article
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Literature Survey of On-chip Architectures and Arbitration Algorithms
Abstract: Today micro-electronic products are influencing the ways of communication, learning and entertainment. The key driving force for the developments during decades is the System-on-Chip (SoC) technologies, where complex applications are integrated onto single ULSI chips. Not only functionally enriched, these products such as mobile phones, notebooks and personal handheld sets are becoming faster, smaller-in-size, larger-in-capacity, lighter-in-weight, lower-in-power-consumption and cheaper. In this survey, communication architectures of SoC are discussed whose design …
Published in Journal of Microcontroller Engineering and Applications · Vol. 4, Issue 1, 2017 · pp. 17–23 Read article
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Implementation of Weighted Round Robin Algorithm in Shared Bus Architectures
Abstract: AbstractThe application domain of System-On-Chips (SoC) includes mobile devices, end terminals, multimedia terminals, automotive, set-top-boxes, games, processors etc. The SoC design paradigm relies heavily on reuse of intellectual property cores, enabling designers to focus on functionality and performance of the overall system. This is possible if IP cores are equipped with highly optimized interface for plug and play insertion into communication architecture. To this purpose the virtual Socket Interface Alliance …
Published in Journal of Electronic Design Technology · Vol. 8, Issue 2, 2017 · pp. 34–40 Read article
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Functional Verification of AMBA AHB-Lite using Layered Testbench Technology of System Verilog
Abstract: Huge complexity of chip increased in the past recent years and integration of more number of transistors on a single system on chip (SoC) makes verification of any SoC based design very critical. Ever increasing complexity and size of designs lead to a number of verification challenges, which are the productivity, efficiency, reusability and completeness. About 75–80 % of the total design cycle time is spent in functional verification. To …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 2, 2016 · pp. 104–112 Read article
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RTL-to-GDS Implementation of a High-Speed On-Chip 32:1 Serializer Using Open-Source Tools
Abstract: Exploring the RTL-to-GDS implementation of a high-speed on-chip 32:1 serializer, this study investigates the integration of open-source tools within VLSI design, emphasizing sustainable practices in the semiconductor industry while operating at the nanometer scale. Addressing methodologies for optimizing power consumption and chip area utilization, particularly focusing on efficient use of non-renewable resources. The study is set against the backdrop of advanced 7nm FinFET technology, critical for enabling efficient data transmission …
Published in Journal of VLSI Design Tools and Technology · Vol. 14, Issue 3, 2024 · pp. 1–10 Read article
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Advancing IoT Connectivity through Very Large-Scale Integration of Semiconductor Technology
Abstract: The term "integrated circuit" as it is currently used typically refers to a monolithic IC, which is significantly different from an HIC in that the former is created by joining several components on a substrate, while the latter is created in a sequence of steps using a single wafer that is subsequently divided into chips. Hybrid chips are perfect for complicated applications in sectors like artificial intelligence (AI), the Internet …
Published in Journal of Semiconductor Devices and Circuits · Vol. 11, Issue 3, 2024 · pp. 54–63 Read article
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A Reliable Routing Architecture and Algorithm for Network-on-Chip
Abstract: The Network-on-Chip (NoC) is Network-version of System-on-Chip (SoC) means that on-chip communication through packet based networks. In NOC topology, routing algorithm and switching are main terminology. The routing algorithm is one of the key factors in NoC architecture. The routing algorithm which defines as the path taken by a packet between the source and the destination. The paper proposes a novel algorithm for a Network-on-Chip, which is based on packet …
Published in Journal of Electronic Design Technology · Vol. 6, Issue 3, 2015 · pp. 40–48 Read article
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Automated Access Backdoor for UVM_REG Layer
Abstract: Systems on chips (SoCs) design have many configuration registers. Configuring the registers through a Bus protocol consumes lot of simulation time. Hence, time saving becomes a challenge in configuring the registers. The other way to configure registers is backdoor access. Backdoor is a zero simulation time access by mapping to the register directly using the hierarchical path. It allows rapid configuration of registers and can uncover hidden bugs as execution …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 2, 2015 · pp. 49–53 Read article
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A Survey on Ultra Low Power Design Techniques for IOT Application
Abstract: AbstractInternet of Things (IOT) is evolving as technology’s megatrend, unlocking new opportunities and questions for the semiconductor industry. IOT sensing and actuation devices essentially should be low cost and also should deliver a complete System on Chip (SOC) solution capable of computation, security and wireless communication at very low power levels. The sub-threshold operation, Radio Frequency (RF) redesign, and extreme optimization techniques can minimize power consumption of IOT devices. This …
Published in Current Trends in Information Technology · Vol. 7, Issue 3, 2017 · pp. 9–16 Read article
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Smart Irrigation Monitoring System
Abstract: AbstractIn this paper we develop a fully Smart Irrigation System based on Node MCU ESP8266 and an IoT app, the BLYNK. Basically, information from a plantation will be captured, temperature and humidity, both of air and soil. Based on those data, then we will decide the right amount (and when) the plantation should receive heat and water. Also, the project should allow manual intervention of an operator in order to …
Published in Current Trends in Signal Processing · Vol. 9, Issue 2, 2019 · pp. 20–22 Read article
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Built in Self Repair for Embedded Memories: A Survey
Abstract: Memory is a significant part of every single computing system. In SOC (System-on-a-chip), 90 to 92% of the total chip zone is enclosed by embedded memories (ITRS 2009) and that means memory density is higher than the logic density. Consequently testing and diagnosis of memories are imperative issues in the SOCs. Revenue of memory is pretentious by the accountabilities present in memory which also distresses the yield of SOC. Built …
Published in Journal of Microelectronics and Solid State Devices · Vol. 2, Issue 1, 2015 · pp. 18–22 Read article
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Hierarchical Methodology Approach to SOC Design: A Comprehensive Look
Abstract: The design scale of a chip has increased many folds in the last few years and shows a continuous exponential trend. This is made possible by the reduction in transistor size and an evolving process technology. As a result, it is possible to move to SoC technology (System on Chip-A single die consisting of multiple subsystems) rather than a traditional ASIC. This has obviously resulted in an increase in the …
Published in Journal of VLSI Design Tools and Technology · Vol. 10, Issue 3, 2020 · pp. 35–42 Read article
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Design of a 4X4 Network-on-Chip Crossbar Router in a System-on-Chip
Abstract: With the number of IPs increasing in an SoC, there is a need for achieving high bandwidth, low latency, scalable multi-core intercommunication and solve the shortcoming of buses. Network-on-chip is a technology which is a solution for such problems. Network-on-chip solves the problem by implementing a communication network of switches, routers and resources. This paper proposes a design for communication among subsystems between intellectual property cores in an SoC design. …
Published in Journal of Microcontroller Engineering and Applications · Vol. 2, Issue 3, 2015 · pp. 28–35 Read article