RTL-to-GDS Implementation of a High-Speed On-Chip 32:1 Serializer Using Open-Source Tools

Abstract

Exploring the RTL-to-GDS implementation of a high-speed on-chip 32:1 serializer, this study investigates the integration of open-source tools within VLSI design, emphasizing sustainable practices in the semiconductor industry while operating at the nanometer scale. Addressing methodologies for optimizing power consumption and chip area utilization, particularly focusing on efficient use of non-renewable resources. The study is set against the backdrop of advanced 7nm FinFET technology, critical for enabling efficient data transmission in modern System-on-Chip (SoC) architectures. The paper intricately delineates the journey from RTL description to physical layout, harnessing the capabilities of Yosys and Open ROAD, prominent open-source tools, in conjunction with the ASAP7 Process Design Kit (PDK). The design achieves optimization in key performance metrics such as power dissipation and chip area utilization, while achieving a remarkable data transmission rate of 17 Gbps. Through meticulous experimentation and analysis, this implementation not only showcases the effectiveness and adaptability of open-source tools in contemporary semiconductor design but also underscores their potential to democratize access and drive innovation in IC development workflows.