STM Journals Peer-reviewed research from Consortium e-Learning Network

Journal of Microcontroller Engineering and Applications

Design of a 4X4 Network-on-Chip Crossbar Router in a System-on-Chip

  1. G Bharat
  2. Guttikonda Bhargav

Abstract

With the number of IPs increasing in an SoC, there is a need for achieving high bandwidth, low latency, scalable multi-core intercommunication and solve the shortcoming of buses. Network-on-chip is a technology which is a solution for such problems. Network-on-chip solves the problem by implementing a communication network of switches, routers and resources. This paper proposes a design for communication among subsystems between intellectual property cores in an SoC design. The specifications of the design are written in HDL and the simulation is done using Synopsys-VCS.

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