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156 articles for “gating design”
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High Performance Multi-Valued Logic (MVL)Gate Design Using FinFET
Abstract: CMOS scaling faces challenges such as leakage, power dissipation, and short channel effects. Multi-Valued Logic (MVL) offers higher information density and reduced interconnections. This work presents a FinFET-based MVL gate design that improves electrostatic control, switching speed, and reliability. Simulation results confirm reduced leakage power and enhanced performance compared to conventional logic. The proposed architecture demonstrates scalability for advanced technology nodes. It also shows potential for low-power applications in portable …
Published in Journal of Microelectronics and Solid State Devices · Vol. 13, Issue 1, 2026 · pp. 34–45 Read article
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Study and Analysis on Multi-gate MOSFET Design
Abstract: AbstractMulti-gate MOSFET is the emerging technology that is used in the area of low-power VLSI design. Multi-gate devices provide much better advantages over conventional MOSFET. As less power dissipation, decrease size, and more operational value could be obtained. Multi-gate MOSFET devices also reduce cost of production. Thus, design of electronics devices based on multi-gate technology is beneficial in today’s requirement. Basic MOSFET due to its reduction in size shows short …
Published in Journal of Semiconductor Devices and Circuits · Vol. 7, Issue 1, 2020 · pp. 1–7 Read article
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Effective Design of Riser for Defect-Free Casting
Abstract: Accurate design of riser helps in producing a defect free casting part. Inaccurate design of riser results in defects like hot spot, shrinkage and blow holes. Present paper focuses on the study of the different parameters occurring during a solidification process, equation which governs the solidification problem and different boundary conditions which play vital role during heat transfer in a solidification process. A literature study is also been conducted in …
Published in Journal of Thin Films, Coating Science Technology & Application · Vol. 4, Issue 2, 2017 · pp. 23–27 Read article
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Application of E-Foundry Based Simulation for the Development of Gating System Design for Endshield FG200 Casting
Abstract: Every casting, by virtue of its geometry, shape, basic material, composition and process has an optimal method. Casting should be designed to achieve controlled progressive directional solidification so that it becomes free from solidification related defects particularly shrinkage porosity. In this research project, endshield FG200 grey casting is being simulated using efoundry for the development of new gating system design. This new gating system ensures directional solidification in casting, thus …
Published in Journal of Mechatronics and Automation · Vol. 4, Issue 3, 2017 · pp. 8–17 Read article
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Verilog-Based Image Processing on Field Programmable Gate Arrays: Design and Implementation
Abstract: Integrated circuits known as Field Programmable Gate Arrays (FPGAs) are frequently offered for sale off the shelf. They are known as "field programmable" because, following manufacture, they enable users to modify the hardware to satisfy particular use case needs. This makes it possible to update features and correct bugs in-place, which is very helpful for remote deployments. Configurable logic blocks (CLBs) and a series of programmable interconnects are features of …
Published in Journal of Semiconductor Devices and Circuits · Vol. 11, Issue 3, 2024 · pp. 13–26 Read article
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Design and Simulation of Ternary Gates Using Fin-FET
Abstract: In recent years, digital communication system has becomes more popular. But the on-chip interconnections have become a major problem as more and more modules are packed into a chip by reducing the gate size. As the gate size is reduced further the complexities in the circuit increases. Binary logic circuit dissipates a lot of energy, increase processing time, and causes coupling effect. In the Ternary logic system, there are three …
Published in Journal of Semiconductor Devices and Circuits · Vol. 2, Issue 3, 2015 · pp. 4–18 Read article
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Power Analysis Comparison of Gated Diode Dram Cell Design on 32 nm Technology
Abstract: In this paper power consumption of Gated diode DRAM (Dynamic Random Access Memory) cells are carried out. This analysis is carried out on 32 nm scale. The DRAM cell used here are 3T1D and 2T1D DRAM cell. Static, total average and transient power for both types of cells are simulated in order to have a comparison of their performance on the same technology. A comparative study of different types of …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 1, 2015 · pp. 19–23 Read article
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Sand Casting Process Optimization via Design of Experiments: A Review
Abstract: Designing and optimizing of gating is an essential part of casting foundry as it contributes significantly to predict and minimize the flow turbulence resulting to casting defects like rough surface, sand inclusion, etc. An Optimization scheme for gating design parameters for casting was proposed with different past studies of the researches. Various designs were modeled and mould filling simulation rooted to minimize turbulence and macro defects are recommended in this …
Published in Trends in Machine design · Vol. 4, Issue 3, 2017 · pp. 1–4 Read article
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Photonic Design of Two Input XOR Gate at 50 Gbps Data Rate
Abstract: This manuscript explores the photonic design of two input XOR gate at 50 Gbps data rate. In the photonic circuit, each component exercised supports for the light wave propagation. The performance of optical XOR gate is alike to their digital variant. The key constituents utilized in designing of this photonic network are 2×2 optical coupler and semiconductor optical amplifier. The proposed design is executed by the igniting the nonlinear attributes …
Published in Journal of Microelectronics and Solid State Devices · Vol. 4, Issue 2, 2017 · pp. 32–39 Read article
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Design and Analysis of Inverters using Double Gate MOSFET
Abstract: AbstractThe double gate MOSFET is a form of MOSFET where two gates are fabricated along the length of the channel, one after another. There are several applications of double gate MOSFETs. It is possible to design logic gates using double gate MOSFETs. It is one of the digital applications of it. This paper interprets the design and analysis of different types of inverters using DG-MOSFET. The advantages of using DG-MOSFET …
Published in Journal of Semiconductor Devices and Circuits · Vol. 4, Issue 1, 2017 · pp. 1–7 Read article
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3D Simulation of Multi-Gate Mosfet Analysis for Analog Circuit Design Parameters
Abstract: Chip density and performance improvements of semiconductor devices have been driven by their aggressive scaling. The performance of multi-gate FET for analog applications is explored in this paper. Analog operation of CMOS devices and its parameters are very important for future cutting edge technologies. The multi-gate technology shows excellent scalability and better immunity to short channel effects in MOSFETs. They are being easily assessed for CMOS applications beyond the 45 …
Published in Journal of Semiconductor Devices and Circuits · Vol. 1, Issue 2, 2014 · pp. 1–8 Read article
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Efficient Analysis and Minimization of Glitches using Threshold Swapped Combinational Clock Gating
Abstract: Nowadays design of electronic circuits to meet requirements like high speed, better functionality and low power is a tedious task. Power dissipation in any circuit comprises mainly two components: static power and dynamic power. The dynamic power heavily depends on the switching activity of the circuit. During the transistor switching transitions some spikes may occur, which are called as glitches. These glitches contribute 20–70% of the dynamic power and 20% …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 2, 2015 · pp. 29–37 Read article
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Concept Design of a Simple Marine Dry Dock (Without Gate)
Abstract: This article explores various options for facilities used in underwater ship repair, including Dry Dock, Ship Lift systems, Floating Dry Docks, and Simple Slipway systems with cradle and winch. Such facilities are crucial to any ship repair operation. Among these, Dry Docks are known for their high capital cost and limited capacity to repair only one ship at a time. This makes them less appealing unless there is substantial demand …
Published in Journal of Offshore Structure and Technology · Vol. 11, Issue 3, 2024 · pp. 46–69 Read article
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Design of FPGA Based ALU Using Reversible Logic Gates
Abstract: Reversible or information misfortune less circuits has applications in computerized signal handling, correspondence, PC design and nanotechnology. Reversible technique is utilized to minimize heat that happens in traditional circuits by keeping the loss of data. This paper proposes a reversible configuration of an ALU. This ALU comprises of eight operations, five are of arithmetic category and three are from logical category operations. An arithmetic operations incorporate add, sub, increase by …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 3, 2016 · pp. 15–21 Read article
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Design and Optimization of Nano scale Double Gate SOI-MOSFET for Analog Applications Using SILVACO TCAD
Abstract: In this paper the structure effect on electrical characteristics of 60-nm double-gate Silicon-on-Insulator Metal-Oxide-Semiconductor Field Effect Transistor (DG-SOI-MOSFETs) is explored. These structures enable more aggressive device scaling in nano scale region because of their ability to control short channel effects. Established a scaling theory which gives guidance for the device optimization (Silicon film thickness Tsi (20nm); gate oxide thickness Tox (3nm); buried oxide thickness Tbox (200nm) and gate length LG …
Published in Journal of Electronic Design Technology · Vol. 1, Issue 1-3, 2011 · pp. 7–17 Read article
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Review Paper To Design a Low Power CNTFET Based XOR Gate
Abstract: The continuous scaling down of Silicon technology leads to various critical challenges and reliability issues such as short channel effect, high leakage current, interconnect problems, etc. CNTFET is the most probable substitutes to traditional MOSFET. The CNTFET device based circuits portray advantages with its better control over the device channel, reduced leakage current, reduced short channel effects. The CNTFET based XOR gate circuits incur the minimum power and energy dissipation. …
Published in Journal of VLSI Design Tools and Technology · Vol. 8, Issue 1, 2018 · pp. 48–53 Read article
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Design of a Verilog HDL-Based Advanced Intelligent Automatic Railway Gate Control System
Abstract: Human mistake, sluggish reaction times, and manual gate operation are common causes of railway level crossing accidents. This project suggests an Intelligent Automatic Railway Gate Controller made with Verilog HDL and simulated in Xilinx Vivado to lessen these mishaps. With the goal of improving safety at unmanned railway crossings, the system is intended to offer a dependable and entirely automated solution. Without human interaction, the railway gate is automatically controlled …
Published in International Journal of Electronics Automation · Vol. 4, Issue 1, 2026 Read article
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Novel approaches to the Design and Optimization of Universal Shift Register with Reversible logic
Abstract: Reversible logic is gaining importance in new multi-disciplinary fields, such as quantum computing, low-power computing, and even nanotechnology. The study of reversible gates has quickly evolved as a distinctive area of research as a result of the new developments aimed at fully utilizing resources and performing operations without any loss of information. With chip integration, these USRs, or Universal Shift Registers, have now become fundamental sequential components needed in various …
Published in Journal of VLSI Design Tools and Technology · Vol. 15, Issue 3, 2025 · pp. 21–28 Read article
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Review of Low Power Johnson Counter
Abstract: Due to the use of clock gating the authors have achieved a power reduction of 37.12 to 41.08% for different frequencies. The authors have run T-Spice simulations for conventional design and clock-gated Johnson counter design. There is a huge difference in the power consumption of the two designs. The clock-gating logic gives this change. And as a 2-input flip-flop is used instead of 3-input flip-flop plays a remarkable role in …
Published in Journal of Microelectronics and Solid State Devices · Vol. 2, Issue 1, 2015 · pp. 13–17 Read article
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Design and Implementation of Low Power Area Effective 2×4 Decoder for SARM Applications Using 16 nm Technology.
Abstract: This project involves analysis of Modified Mixed Logic Design abbreviated as MMLD which includes following design logics: Complementary Metal Oxide Semiconductor abbreviated to CMOS logic design, Gate Diffusion Input abbreviated as GDI technique, and Dual Value Logic called as DVL. Two logic styles are used in this paper study to reduce power dissipation and delay time which are fourteen 14-transistor and fifteen 15-transistor decoders. Every situation requires the use of …
Published in Journal of Semiconductor Devices and Circuits · Vol. 10, Issue 1, 2024 · pp. 24–36 Read article