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36 articles for “digital arithmetic”
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Design of a Modified Low Power PTL based 64-Bit Comparator
Abstract: In this paper, we have presented comparison of modified and existing 64-bit binary comparator designs concentrating on power consumption, delay and PDP. Modifications are done in existing 64-bit binary comparator design to improve the PDP of the proposed design. The modified design have been performed by using PTL logic in existing 64-bit binary comparator design to improve the speed of the circuit. Comparison between modified and existing 64-bit binary comparator …
Published in Research & Reviews: A Journal of Embedded System & Applications · Vol. 2, Issue 3, 2014 · pp. 10–17 Read article
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Low-Power Reconfigurable Digital Filter Design Using FPGA for IoT Edge Devices
Abstract: The rapid evolution of the Internet of Things (IoT) has led to an exponential increase in the deployment of edge devices that continuously process real-time sensor data under strict power, latency, and computational constraints. Digital filtering remains a critical operation in these devices, supporting tasks such as noise removal, data conditioning, and feature extraction for intelligent decision-making. However, conventional filter implementations on microcontrollers or fixed digital signal processors often struggle …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 3, Issue 2, 2025 · pp. 23–34 Read article
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High Throughput RISC Processor Design Using Vedic Mathematics: A Review
Abstract: The load on general processor is increasing. It is of the utmost importance in the arithmetic unit for fast operations. Multipliers have a significant impact on how well the Arithmetic Unit performs. In this way, analysts are constantly looking for new methodologies and equipment to execute number juggling activity in tremendous proficient manner in the terms of speed and region. Vedic Science is the old arrangement of math which has …
Published in Research & Reviews: A Journal of Embedded System & Applications · Vol. 10, Issue 2, 2022 · pp. 29–33 Read article
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Design and Implementation of Carry Select Adder based On Wallace tree Multiplier using Adiabatic Logic
Abstract: The Wallace tree multiplier construction using a carry select adder (CSA) and this paper discusses adiabaticlogic. The proposed design aims to reduce power consumption while maintaining high performance.Adiabatic logic is employed to reduce power dissipation by recycling energy during the logic transitions. TheWallace tree multiplier is used to perform fast multiplication of two large numbers by breaking down themultiplication process into smaller sub-tasks. The CSA is used as the adder …
Published in Journal of VLSI Design Tools and Technology · Vol. 13, Issue 2, 2023 · pp. 21–31 Read article
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Design and Validation of Low Power High Speed area effective comparator using CMOS Technology
Abstract: The most fundamental arithmetic comparisons in a digital comparator involve comparing two numbers that are greater than, less than, or equal to each other. While doing enormous level arithmetic comparisons, a digital comparator needs more space, which results in higher power consumption and a delayed response. This can be solved by using N-bit comparator with two modules using 45GPDK CMOS Technology. An N-bit comparator can operate at extremely high speeds …
Published in Recent Trends in Electronics Communication Systems · Vol. 10, Issue 2, 2023 · pp. 20–29 Read article
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Implementation of Carry Select Adder with Reduced Area Scheme
Abstract: Addition is the heart of arithmetic unit and the arithmetic unit is often the work horse of a computational circuit. So, adders play a key role in designing an arithmetic unit and also many digital integrated circuits. Carry select adder (CSLA) is one of the fastest adders used in many data processors and in digital circuits to perform arithmetic operations. But CSLA is area-consuming because it consists of dual ripple …
Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 1, 2017 · pp. 1–5 Read article
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Design and Implementation of 256-bit Vedic Multiplier on Reconfigurable Platform
Abstract: Multiplication is a fundamental arithmetic operation in digital signal processing and embedded systems. Traditional multiplier architectures often suffer from increased latency and resource utilization when scaled to higher bit widths. Vedic Mathematics, an ancient Indian technique, offers a novel and efficient alternative. This paper presents the design and implementation of a 256-bit Vedic multiplier using the Urdhva Tiryakbhyam Sutra on a reconfigurable hardware platform, specifically FPGA. The proposed architecture decomposes …
Published in Journal of Materials & Metallurgical Engineering · Vol. 15, Issue 3, 2025 · pp. 56–65 Read article
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Design and Simulation of 4-bit Multiplier using Carry Look-Ahead Adder at Transistor Level
Abstract: Multiplication is a basic operation performed in the Arithmetic Logic Unit, Digital signal processing, Floating-point unit and Application specific integrated circuits. This paper deals with the design and simulation of the 4-bit multiplier using a carry look-ahead adder at the transistor level. The total design process involves hierarchical implementation. Where the basic gate operations like AND, OR, NOT, and XOR are repeatedly used for designing the entire circuit. So, the …
Published in Journal of VLSI Design Tools and Technology · Vol. 11, Issue 3, 2021 · pp. 10–18 Read article
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Study And Literature Analysis of The Coarse-Grained Logic Interface with Floating-Point Arithmetic Unit
Abstract: Field-Programmable Gate Arrays (FPGAs) have become an essential digital circuit implementation techni que. The research looks at the design parameters by evaluating the building of an arithmetic logic unit (ALU) in Xilinx Vivado utilizing Hardware Description Language (HDL) and implementing common Field Programmable gate arrays (FPGAs). The ALU is a logic design component in digital computers that seeks to deliver optimal algorithms to maximize the usage of available hardware. The …
Published in Journal of VLSI Design Tools and Technology · Vol. 13, Issue 2, 2023 · pp. 45–55 Read article
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64 Bit ALU DESIGN USING VEDIC MATHEMATHICS
Abstract: High-speed arithmetic operations are crucial for better performance in contemporary digital systems. Particularly for high bit-width operations, conventional arithmetic logic units (ALUs) frequently experience increased latency and complexity. This work presents the design and implementation of a 64-bit Arithmetic Logic Unit (ALU) using notions from Vedic mathematics. The suggested design makes use of a Kogge-Stone Adder for effective addition and the Urdhva Tiryagbhyam sutra for quick multiplication. Among other mathematical …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 4, Issue 1, 2026 Read article
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An Area Delay Optimized Carry-Select Adder
Abstract: In arithmetic and logic unit of digital signal processor (DSP), adder is the important hardware unit. Carry select adder (CSLA) is the best example of the adder used in DSP and it is widely used in many data processors to increase speed. So, the adder performance affects the overall system-performance. The Regular Square root (SQRT) CSLA consists of two Ripple Carry Adders (RCA), so it consumes more area due to …
Published in Journal of VLSI Design Tools and Technology · Vol. 8, Issue 3, 2018 · pp. 10–14 Read article
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Comparative Study of Psychomotor Performance in Depression Patients with Healthy Volunteers
Abstract: Antidepressant drug therapy can affect psychomotor performance of patients suffering from depression. Hence, the present study was planned to assess the psychomotor performance of under therapy depression patients with healthy volunteers using battery of psychometric tests. Twenty under therapy patients suffering from depression and taking antidepressant drugs treatment for not less than six months were compared with 20 healthy volunteers. The psychometric test battery included three subjective visual analogue scales …
Published in Research and Reviews : A Journal of Medical Science and Technology · Vol. 2, Issue 1, 2013 · pp. 15–18 Read article
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Assessment of Psychomotor Performance of Under-therapy Patients Suffering from Schizophrenia with Healthy Volunteers
Abstract: Patients suffering from psychiatric disorders like schizophrenia and depression usually exhibit impaired psychomotor performance. Drug therapy can also affect their psychomotor performance. Therefore, present study was conducted to assess the psychomotor performance of such cases so that if there is any impairment, it can be detected, using battery of psychometric tests. In the present study, 20 schizophrenia patients taking drug therapy for not less than six months were compared with …
Published in Research and Reviews: A Journal of Medicine · Vol. 3, Issue 1, 2013 · pp. 8–11 Read article
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A Novel Design for High Speed & Area Efficient Compressor Based Vedic Multiplier
Abstract: Multipliers are the most important part in any arithmetic and logic unit, AbstractMultipliers are the most important part in any arithmetic and logic unit, accumulators and digital signal processors. Due to the increasing constraints on delay, the design of faster multipliers is emphasized. Among several multipliers, Vedic multipliers are preferred for their speed of operation. Here the proposed Vedic multiplication techniques are based on “URDHVA TIRYAKBHYAM” a fast and efficient …
Published in Journal of Microelectronics and Solid State Devices · Vol. 5, Issue 3, 2018 · pp. 1–10 Read article
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Reducing Crosstalk in Arithmetic and Logic Unit Part of a Processor
Abstract: Crosstalk is common in any digital systems and may occur due to coupling of signals which eventually have an impact on the working of a system. In this paper, an attempt is made to study the effect of crosstalk in 8-bit slice ALU, designed using 120 nm technology and suggested a method to reduce the crosstalk.Keywords: ALU, signal integrity, metal layers
Published in Journal of VLSI Design Tools and Technology · Vol. 3, Issue 1, 2013 · pp. 28–32 Read article
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High Speed and Low Area Energy Efficient FPGA Implementation using RSD based Elliptic Curve Cryptography
Abstract: In this paper we will study high speed energy efficient FPGA implementation using redundant sign digit elliptic curve cryptography. In existing system to design processor with high area and low speed computation process so that we proposed to low area with high speed computation using Elliptical cryptography processor. Here we use redundant signed digit to reduce the overhead due to computations. For modular arithmetic operation for multiplication, we used Karatsuba-Ofman …
Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 3, 2017 · pp. 45–50 Read article
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High Speed and Low Area Energy Efficient FPGA Implementation using RSD based Elliptic Curve Cryptography
Abstract: In this paper we will study high speed energy efficient FPGA implementation using redundant sign digit elliptic curve cryptography. In existing system to design processor with high area and low speed computation process so that we proposed to low area with high speed computation using Elliptical cryptography processor. Here we use redundant signed digit to reduce the overhead due to computations. For modular arithmetic operation for multiplication, we used Karatsuba-Ofman …
Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 2, 2017 · pp. 45–50 Read article
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Design and Implementation of High Speed and Low Power 88 Bit Array Multiplier
Abstract: The main objective of this paper is to design and implement simple, suitable and reliable multipliers for digital signal processors, Math processors, digital filters, and ALU. Multipliers are one of the leading arithmetic units in Microprocessors and DSPs and also a major source of power consumption. The key objective of this work is to measure the average power consumption and delay of 8´8 array multiplier. The design of full adder …
Published in Journal of Microcontroller Engineering and Applications · Vol. 2, Issue 3, 2015 · pp. 1–7 Read article
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Design And Optimization Of High-Speed Array Multiplier
Abstract: An array multiplier is a digital circuit used for the rapid multiplication of binary numbers. It employs an array of logic gates to generate partial products concurrently, significantly enhancing speed. The array structure divides the multiplication task into smaller, parallel processes, allowing for efficient parallel processing of multiple bits. Each cell within the array manages specific bit-level multiplications, and their results are summed to produce the final product. This parallel …
Published in Journal of Microelectronics and Solid State Devices · Vol. 11, Issue 3, 2024 Read article
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Management of Team Work in a Digital Age for Sports Programme Effectiveness in Public Senior Secondary Schools in Rivers State, Nigeria
Abstract: This study was basically on the management of team work in a digital age for sports programme effectiveness in public senior secondary schools in Rivers State, Nigeria. A descriptive survey research design was adopted. The population comprised all 286 principals and 572 sports officials across the public senior secondary schools in the state. A sample size of 429 respondents was selected using a stratified random sampling technique. Data collection was …
Published in Recent Trends in Sports · Vol. 3, Issue 2, 2026 · pp. 8–13 Read article