The main objective of this paper is to design and implement simple, suitable and reliable multipliers for digital signal processors, Math processors, digital filters, and ALU. Multipliers are one of the leading arithmetic units in Microprocessors and DSPs and also a major source of power consumption. The key objective of this work is to measure the average power consumption and delay of 8´8 array multiplier. The design of full adder for low power is obtained and the low power units are implemented on the proposed multiplier and the results are analyzed for better performance. The design has been implemented and are simulated using PTM 45nm CMOS process technology in Tanner Sedit V.15 tool. Keywords: Array Multiplier Architecture, 8´8 Bit Array, Implementation, SimulationCite this Article Bharat H. Nagpara, Design and Implementation of High Speed and Low Power 8´8 Bit Array Multiplier, Journal of Microcontroller Engineering and Application. 2015; 2(3): 1–7p.
