In this paper, we have presented comparison of modified and existing 64-bit binary comparator designs concentrating on power consumption, delay and PDP. Modifications are done in existing 64-bit binary comparator design to improve the PDP of the proposed design. The modified design have been performed by using PTL logic in existing 64-bit binary comparator design to improve the speed of the circuit. Comparison between modified and existing 64-bit binary comparator designs is calculated by simulation that is performed at 180 nm technology in Tanner EDA Tool. Keywords: Binary comparator, digital arithmetic, power delay product, PTL, power, area
