Binary comparator
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Design of a Modified Low Power PTL based 64-Bit Comparator
Abstract: In this paper, we have presented comparison of modified and existing 64-bit binary comparator designs concentrating on power consumption, delay and PDP. Modifications are done in existing 64-bit binary comparator design to improve the PDP of the proposed design. The modified design have been performed by using PTL logic in existing 64-bit binary comparator design to improve the speed of the circuit. Comparison between modified and existing 64-bit binary comparator …
Published in Research & Reviews: A Journal of Embedded System & Applications · Vol. 2, Issue 3, 2014 · pp. 10–17 Read article