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595 articles for “Processing Speed”
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Enhancing Secure Communication Through Hybrid Steganography and Public Key Cryptography
Abstract: This research pioneers an innovative paradigm in secure data communication by seamlessly merging Public Key Digital Image Steganography with public key cryptography. The proposed method leverages the formidable strength of the RSA algorithm, employing a robust 1024-bit key size for secure data encryption. In parallel, the imperceptibility of the F5 steganographic technique is harnessed to clandestinely embed the encrypted message within a cover image. Unlike conventional methods, our scheme introduces …
Published in Journal of Mobile Computing, Communications & Mobile Networks · Vol. 10, Issue 3, 2023 · pp. 38–46 Read article
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ARM Processor Based Speed Control of Motor
Abstract: The electric autos at that point hit the streets, furthermore, have denoted the start for electric vehicle period. Additionally it may be a zero emission, earth inviting vehicle. This paper describes the accurate control of speed without gearing system. Our recommended vehicle need been intended to show exact speed controlling and additionally simple turning purpose for electrical vehicles utilizing four engine drive frameworks. The gadget permits the client to send …
Published in Journal of Advances in Shell Programming · Vol. 6, Issue 1, 2019 · pp. 8–13 Read article
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Study and analysis of the Double Data Rate SDRAM Controller for High-speed Interfacing with Processing Device
Abstract: A real-time embedded system must now manage many programs running concurrently. Increased Data Rate Because of its burst access, speed, and pipeline features, synchronous DRAM is a typical memory-building material. DDR transfers are performed using synchronous dynamic access memory. The memory controller must be set with a pipelined design for various applications and systems to perform effectively. The purpose of this study is to design a DRAM controller that will …
Published in Journal of VLSI Design Tools and Technology · Vol. 14, Issue 1, 2024 · pp. 8–13 Read article
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Optimizing Image Processing with Verilog on FPGA: Techniques and Performance Enhancements
Abstract: The integration of image processing algorithms into hardware platforms, particularly FPGAs, presents a compelling opportunity for achieving high performance, low latency, and power efficiency in real-time applications. This study focuses on designing and implementing Verilog HDL-based optimal image processing methods for FPGA-based systems. The study explores the development of core algorithms, including edge detection, image enhancement, and adaptive filtering, to maximize resource utilization and processing speed on hardware platforms. Key …
Published in Journal of Semiconductor Devices and Circuits · Vol. 11, Issue 3, 2024 · pp. 46–53 Read article
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Advances in Speed Control Techniques for Three-phase Induction Motors
Abstract: Induction motors are pivotal in modern industrial applications due to their efficiency and adaptability. Electric motors that run on alternating current (AC) and are driven by a rotating magnetic field are called induction motors. They consist of coils that use electromagnetic induction to transform electrical energy into mechanical energy, a rotor, and a stator. AC induction motors are incredibly adaptable, efficient, and have a comparatively straightforward construction. This paper provides …
Published in Journal of Control & Instrumentation · Vol. 15, Issue 3, 2024 · pp. 1–8 Read article
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A Novel Efficient VLSI Architecture of Modified 16B SQRT Carry Select Adder:A Review
Abstract: Due to advancement of new technology in the field of VLSI and Embedded system, there is an increasing demand of high speed and low power consumption processor. Speed of processor greatly depends on its multiplier as well as adder performance. Due to which high speed adder architecture become important. Several adder architecture designs have been developed to increase the efficiency of the adder. In this paper, we introduce an architecture …
Published in Research & Reviews: A Journal of Embedded System & Applications · Vol. 3, Issue 2, 2015 · pp. 23–26 Read article
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A Novel Efficient VLSI Architecture for Matrix Multiplication using Compressor-based Multiplier
Abstract: Due to advancement of new technology in the field of VLSI, there is an increasing demand of high speed processor. Matrix multiplication is highly used in different types of computations. Speed of processor greatly depends on its multiplier (used in matrix multiplication) performance. Due to which high speed multiplier architecture become important. Several multiplication techniques have been developed to increase the efficiency of the multiplier. These techniques help in reducing …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 2, 2015 · pp. 23–28 Read article
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Vector Signal Transceiver (VST) in LabVIEW: A Review
Abstract: AbstractOver the past few decades, the increasingly popular architecture of RF systems with software has become increasingly popular. Almost every commercial automated RF system (COTS) today uses application software for communication via the bus interface with the device. As the complexity of radio frequency applications is increasing, engineers are constantly faced with the dilemma of increasing functionality without increasing testing time and, ultimately, to verify the cost. Although improvements in …
Published in Journal of Telecommunication, Switching Systems and Networks · Vol. 5, Issue 1, 2018 · pp. 1–5 Read article
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VHDL Implementation of 4 Bit Multipliers: Comparative Study with Vedic Multiplier
Abstract: The multiplier and adder are the basic building blocks of ALU of any processor and speed of this processor are greatly depends on these building blocks. The performance of multipliers can be analyzed using its performance parameters like speed, power consumption, complexity, etc. In digital signal processors as well as in general processors high speed can be achieved using this multiplier block. The Vedic multiplier architecture exhibits speed improvements and …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 3, 2015 · pp. 122–127 Read article
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A Triad Frame Approach for Assessment of Evacuation Speed of the Evacuee during Emergency Evacuation in Process Industry
Abstract: The assessment of the safety level of industry during emergency is the core of fire safety engineering as well as in people’s safety. According to the performance based design approach, this task can be addressed by calculating the available speed, which is the from ignition to the moment when the condition of the given environment become untenable and the speed needed by evacuee to escape safely which is known in …
Published in Journal of Industrial Safety Engineering · Vol. 8, Issue 3, 2021 · pp. 24–30 Read article
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Effect of Hot Induction Process on Bend Properties
Abstract: This paper discusses about the effect of processing speed and water flow rate on the mechanical properties of the hot induction bending of grade API5LX70 for the bending angle of 30o with the bending radius of 3D. Water flow rate & speed of the bending machine were varied to optimize the process parameters with respect to mechanical properties.
Published in Journal of Materials & Metallurgical Engineering · Vol. 2, Issue 1-3, 2012 · pp. 97–104 Read article
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Automated Car License Plate Detection and Recognition Using Deep Learning
Abstract: The use of automated license plate detection and recognition (ALPR) systems to automate processes such as number plate detection is gaining popularity in traffic control, security, and law enforcement. This research focuses on achieving more accurate and efficient detection and recognition of number plates by leveraging deep learning techniques. The systems outlined in this study aim to improve the effectiveness of ALPR systems using advanced convolutional neural networks (CNNs) and …
Published in Journal of Image Processing & Pattern Recognition Progress · Vol. 13, Issue 1, 2026 · pp. 23–29 Read article
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An Optimized 32 bit Carry Select Adder Using Modified BEC
Abstract: AbstractAdders play a major role in addition of numbers, multiplications and other advanced processors’ design. Among the conventional adder structures, carry select adder is known to be fastest adder. This adder circuit is used for the design of high speed processors. The CSLA adder architecture is such that it is of less power dissipation, area efficient and high speed. CSLA circuit for 8, 16, 32 bits is designed without multiplexer …
Published in Journal of Semiconductor Devices and Circuits · Vol. 5, Issue 2, 2018 · pp. 27–32 Read article
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High Speed and Low Area Energy Efficient FPGA Implementation using RSD based Elliptic Curve Cryptography
Abstract: In this paper we will study high speed energy efficient FPGA implementation using redundant sign digit elliptic curve cryptography. In existing system to design processor with high area and low speed computation process so that we proposed to low area with high speed computation using Elliptical cryptography processor. Here we use redundant signed digit to reduce the overhead due to computations. For modular arithmetic operation for multiplication, we used Karatsuba-Ofman …
Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 3, 2017 · pp. 45–50 Read article
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Challenges in Parallel Computing for Big Data Analytics
Abstract: The integration of parallel computing into the realm of big data analytics promises accelerated processing speeds and enhanced scalability, but it is not without its formidable challenges. This study explores the multifaceted hurdles faced in the pursuit of efficient parallel processing for large-scale data analytics. The intricate task of distributing and partitioning massive datasets across multiple processing units demands adept strategies to ensure equitable workloads. Load balancing emerges as a …
Published in Recent Trends in Parallel Computing · Vol. 11, Issue 1, 2024 · pp. 1–6 Read article
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Design of Optimized Full Adder using Noise-Mitigation Techniques and Power Gating
Abstract: With the advent of nanoscale technology, a new era of power consumption, speed, and reliability challenges for traditional static CMOS logic has begun. To solve these problems, dynamic logic families—particularly domino logic—have emerged as potent substitutes that offer quicker processing speeds and lower power consumption. The design and optimization of a full adder circuit using domino logic is shown in this study. A dynamic domino logic technique is used to …
Published in Journal of Microelectronics and Solid State Devices · Vol. 11, Issue 3, 2024 · pp. 1–6 Read article
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MAC Unit Implementation on FPGA
Abstract: Multiply–accumulate (MAC) computations account for a large part of machine learning accelerator operations. The pipelined structure is usually adopted to improve the performance by reducing the length of critical paths. An increase in the number of flip-flops due to pipelining, however, generally results in significant area and power increase. Using this method, we create and build a cutset-free feedforward MAC architecture that maximizes data propagation and removes superfluous pipeline registers. …
Published in Journal of Microcontroller Engineering and Applications · Vol. 13, Issue 1, 2026 · pp. 29–37 Read article
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Application of Ultrasound for Synthesis of Biodiesel
Abstract: The aim of study is to synthesize a biodiesel from soybean oil using ultrasonic process. At present, biodiesel is produced in batch reactors in which the required energy is provided by heating by mechanical mixing. Alternatively, ultrasonic processing is an effective way to attain required mixing providing the necessary activation energy. Ultrasonic is a very desirable tool for producing biodiesel from vegetable oil and animal fats, because it lowers the …
Published in Emerging Trends in Chemical Engineering · Vol. 2, Issue 1, 2015 · pp. 1–8 Read article
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Design of Single Bitline Novel 5T SRAM Cell to Reduce The Power Dissipation Using Cadence
Abstract: Fast growing field of IC technology is persistently demanding for low power consumption and efficient solution. Most of the available SRAM designs are based on standard 6T SRAM cell in addition to other circuit and transistors count. A novel 5T CMOS SRAM is presented in this paper, for simultaneously minimizing power consumption and an improving process speed. The presented unique 5T SRAM cell employs single bitline for read/write function. Implementation …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 1, 2016 · pp. 49–54 Read article
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High Speed and Low Area Energy Efficient FPGA Implementation using RSD based Elliptic Curve Cryptography
Abstract: In this paper we will study high speed energy efficient FPGA implementation using redundant sign digit elliptic curve cryptography. In existing system to design processor with high area and low speed computation process so that we proposed to low area with high speed computation using Elliptical cryptography processor. Here we use redundant signed digit to reduce the overhead due to computations. For modular arithmetic operation for multiplication, we used Karatsuba-Ofman …
Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 2, 2017 · pp. 45–50 Read article