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18 articles for “Double gate MOSFETs”
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Design and Analysis of Inverters using Double Gate MOSFET
Abstract: AbstractThe double gate MOSFET is a form of MOSFET where two gates are fabricated along the length of the channel, one after another. There are several applications of double gate MOSFETs. It is possible to design logic gates using double gate MOSFETs. It is one of the digital applications of it. This paper interprets the design and analysis of different types of inverters using DG-MOSFET. The advantages of using DG-MOSFET …
Published in Journal of Semiconductor Devices and Circuits · Vol. 4, Issue 1, 2017 · pp. 1–7 Read article
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GaN-based Double Gate MOSFET (DG-MOSFET)
Abstract: AbstractGaN is auspicious for high-power, high-temperature devices because of its large bandgap, and high saturation velocity compared with Si. Gallium nitride (GaN) based devices are expected to play an important role to develop the next-generation devices. The performance of GaN-based double gate (DG) MOSFETs have been explored with gate length (Lg) 10.6 nm. The ON-current (ION) and OFF-current (IOFF) are found to be 8.11´10–3 and 6.38605´10–9A/µm respectively, respectively with an …
Published in Journal of Semiconductor Devices and Circuits · Vol. 5, Issue 3, 2018 · pp. 24–28 Read article
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Quantum Behavior of Charge Carriers in a Symmetrical Double Gate MOSFET
Abstract: Our earlier work on modeling of single gate n-channel metal oxide semiconductor field effect transistor (MOSFET) has been extended to discuss the quantum behavior of charge carriers in symmetrical double gate (DG) MOSFET. The potential profile in the channel region of DG MOSFET has been obtained in parabolic approximation. The parabolic potential facilitates analytical expression for electric field. The appropriate Schrodinger’s equation has been solved to obtain wave functions in …
Published in Journal of VLSI Design Tools and Technology · Vol. 11, Issue 1, 2021 · pp. 17–28 Read article
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Sub-nano Regime DG-MOSFETs
Abstract: AbstractThe significance of device performance of Gallium Nitride based double gate metal-oxide- semiconductor field-effect-transistor has been executed. The simulations were done by Silvaco Atlas simulation software with focusing on non-equilibrium green function (NEGF). Multiple gate length (LG=9.1 nm) was observed to distinguish the transfer characteristics curve. The other concentration was observed for device ON-State Current (ION), OFF-State Current (IOFF), Drain Induced Barrier Lowering (DIBL), Sub Threshold Slope (SS) and Electric …
Published in Journal of Semiconductor Devices and Circuits · Vol. 5, Issue 3, 2018 · pp. 1–6 Read article
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Design and Optimization of Nano scale Double Gate SOI-MOSFET for Analog Applications Using SILVACO TCAD
Abstract: In this paper the structure effect on electrical characteristics of 60-nm double-gate Silicon-on-Insulator Metal-Oxide-Semiconductor Field Effect Transistor (DG-SOI-MOSFETs) is explored. These structures enable more aggressive device scaling in nano scale region because of their ability to control short channel effects. Established a scaling theory which gives guidance for the device optimization (Silicon film thickness Tsi (20nm); gate oxide thickness Tox (3nm); buried oxide thickness Tbox (200nm) and gate length LG …
Published in Journal of Electronic Design Technology · Vol. 1, Issue 1-3, 2011 · pp. 7–17 Read article
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A Two-Dimensional (2D) Analytical Model for Channel Potential and Threshold Voltage of Short Channel Triple Material Gate-Double Halo (TMG-DH) DG MOSFET
Abstract: In the present paper, an analytical model for the channel potential of short channel Triple Material Gate-Double Halo (TMG-DH) DG MOSFET has been presented using parabolic approximation method. Further, the threshold voltage of the device has been calculated using minimum mid channel potential and the result obtained has been compared with the threshold voltage of Triple Material double gate (TMDG) MOSFET in order to show the improvement in the threshold …
Published in Journal of Microelectronics and Solid State Devices · Vol. 6, Issue 2, 2019 · pp. 13–25 Read article
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Comparative Study of Drain Current of Symmetric and Asymmetric DG-MOSFET with Simulation in Silvaco TCAD Software
Abstract: One of the most attractive and promising devices for the nanoscale devices is the double gate MOSFET. The double gate MOSFET can control the Si channel very efficiently and it chooses a very small width of the Si channel. It controls the Si channel by applying gate contact to either side of the channel. The idea of controlling the S channel in such a way reduces the short channel effects …
Published in Journal of Semiconductor Devices and Circuits Read article
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Influence of Graded Channel on Performance of Symmetric Double Material Gate Insulator FDSOI MOSFET
Abstract: Abstract: In this paper, we investigate the effect on the linearity, analog and RF performance of graded channel in case of hetero-gate-dielectric FDSOI MOSFET with higher doping at source end and low doping at drain end. The major figure of merits (FOMs) studied are on-state drive current (ION), transconductance (gm), total gate capacitance (Cgg), cut-off frequency (fT), higher order derivative of transconductance (gm’, gm’’), intermodulation distortion (IMD3) and third- order …
Published in Journal of Microelectronics and Solid State Devices · Vol. 6, Issue 1, 2019 · pp. 12–17 Read article
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Comparative study of Drain current of Symmetric and Asymmetric DGMOSFET with simulation in Silvaco_TCAD Software
Abstract: For nano regime devices the double gate MOSFET is one of the most promising and attractive devices. The main idea of a Double Gate MOSFET is to control the Si channel very efficiently by choosing the Si channel width to be very small and by applying a gate contact to both sides of the channel. This concept helps to suppress short channel effects and leads to higher currents as compared …
Published in Journal of Semiconductor Devices and Circuits · Vol. 8, Issue 1, 2021 · pp. 1–13 Read article
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Advanced Mathematical Modelling of Nanoscale Semiconductor Devices for Low-Power Microelectronic Applications
Abstract: With the ongoing scaling down of semiconductor devices, there is an increasing need for accurate mathematical models of electrostatic control, carrier transport, leakage current, and power consumption at the nanometer scale. As the sizes of semiconductors continue to decrease, there is a growing need for accurate mathematical models of electrostatic control, carrier transport, leakage current, and power consumption at the nanometer scale. In this work, a common mathematical modelling approach …
Published in Journal of Microelectronics and Solid State Devices · Vol. 13, Issue 2, 2026 Read article
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Impact of Source/Drain Engineering on Performance of Single Gate and Dual Gate Junctionless MOSFET
Abstract: Abstract: This letter is the study on impact of source/drain engineering on Single Gate (SG) and Dual Gate (DG) Junctionless MOSFET. Both the proposed MOSFET have Gate Stacking and highly doped source/drain region, so name suggested is Highly Doped Source Drain Gate Stack Junctionless (HDSD-GSJL) MOSFET. Here we investigate the effect of highly doped source/drain, gate stacking and double gate on junctionless MOSFET. The investigation is performed in relations of …
Published in Journal of Semiconductor Devices and Circuits · Vol. 6, Issue 1, 2019 · pp. 10–14 Read article
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Comparative Analysis of FD-DMDG SON MOSFET over FD DMDG SOI MOSFET
Abstract: AbstractIn the recent past, Silicon-on-Insulator (SOI) shows better device performance in comparison to bulk Silicon devices but it still suffers from different short channel effects (SCEs). Recently a structure, Silicon on Nothing (SON), has been suggested and investigated. It is structured to be capable of substantial reduction of SCEs and present better electrical characteristics in comparison to SOI. The absence of the buried layer results in the reduced electrostatic coupling …
Published in Journal of Electronic Design Technology · Vol. 9, Issue 1, 2018 · pp. 9–16 Read article
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Simulation Study of Process Variations in Double Gate Junctionless Field-Effect Transistors
Abstract: This work discusses the process variations in symmetrical double-gate (DG) junctionless (JL) field-effect transistors (FETs) by device simulation. Output I-V characteristics along with subthreshold slope increase, DIBL variations with drain voltage and threshold voltage shift variations are systematically analyzed with the general variability issues including oxide thickness, channel thickness and doping concentration. Potential distribution in the body channel region is also analyzed. Optimum values of the variability factors are considered …
Published in Journal of Semiconductor Devices and Circuits · Vol. 2, Issue 2, 2015 · pp. 18–27 Read article
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Detailed Study of Working and Applications of FinFET Technology and Its Adaptability in Current Era
Abstract: The CMOS technology is following Moore’s law since almost 25 years. The scaling of CMOS transistor has increased packaging density, speed and decreased power dissipation in the integrated circuits. However, CMOS dimension when scaled to nanometer dimension, many physical barriers arise. In sub-100 nm scale, MOSFET has new variants as SOI implementation and double gate. Keywords: Silicon on insulator (SOI), short channel effect (SCE) [2], buried oxide (BOX)
Published in Journal of VLSI Design Tools and Technology · Vol. 2, Issue 1-2-3, 2012 · pp. 52–58 Read article
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Design and Performance Analysis of Full Adder Cell using FinFET Technique at 32nm Technology
Abstract: AbstractIn this paper, discussed is the comparative analysis of complementary MOS (CMOS) and dual gate-FinFET (fin shaped field effect transistor) based full adder cell design. To reduce the average power, average current and maximum current of 1-bit full adder circuit a new high DG-FinFET technique is presented. Use of double-gate FinFET technology provides low leakage and high performance operation. For MOSFET transistor model, a predictive technology model (PTM) BSIM4 and …
Published in Journal of Microelectronics and Solid State Devices · Vol. 4, Issue 3, 2017 · pp. 1–8 Read article
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Performance Analysis of 3T DRAM Using FinFET Based with Leakage Reduction Techniques at 45 nm Technology
Abstract: The proposed area of research is to reduce the power consumption, leakage voltage, leakage current and leakage power of DRAM while maintaining the competitive performance. The Fin FET approach is used in DRAM for high performance. Fin type field effect transistors (Fin FET) are capable substitutes for bulk CMOS at the nano-scale. Fin FET are double gate device. A Fin FET uses an intrinsic body. It greatly suppresses the device-performance …
Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 3, 2017 · pp. 28–34 Read article
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Performance Analysis of 3T DRAM Using FinFET Based with Leakage Reduction Techniques at 45 nm Technology
Abstract: The proposed area of research is to reduce the power consumption, leakage voltage, leakage current and leakage power of DRAM while maintaining the competitive performance. The Fin FET approach is used in DRAM for high performance. Fin type field effect transistors (Fin FET) are capable substitutes for bulk CMOS at the nano-scale. Fin FET are double gate device. A Fin FET uses an intrinsic body. It greatly suppresses the device-performance …
Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 2, 2017 · pp. 28–34 Read article
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A Dual Material Control Gate Tunnel Field Effect Transistor for an Asymmetric Doping at Source and Drain Regions
Abstract: Double-Gate tunnel FET devices, which uses high-κ gate dielectric, are explored using realistic design parameters, showing an ON-current as high as 0.23 mA, a gate voltage of 1.8 V, an OFF-current of not more than 1 fA (neglecting gate leakage), an improved ordinary subthreshold swing of 57 mV/dec, and a lower point slope of 11 mV/dec. A dual material control gate tunnel field effect transistor for an asymmetric doping at …
Published in Journal of VLSI Design Tools and Technology · Vol. 8, Issue 3, 2018 · pp. 45–53 Read article