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153 articles for “CMOS design”
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A Comprehensive Review of CMOS Analog Circuit Design Techniques for Low-Power VLSI Systems
Abstract: CMOS analog circuit design plays a significant role in the development of modern low-power Very Large-Scale Integration (VLSI) systems used in wireless communication, biomedical devices, portable electronics, embedded systems, and Internet of Things (IoT) applications. Research on low-power CMOS analogue design methodologies has intensified because to the growing need for high-performance, small, and energy-efficient electronic products. However, reducing power consumption while maintaining signal accuracy, noise performance, stability, bandwidth, and overall …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 4, Issue 1, 2026 Read article
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Design of CMOS AM Modem for Wireless Sensors
Abstract: A design of amplitude modulated (AM) modem, compatible to CMOS technology for its monolithic integration with either wireless microsensors or other sources of baseband signals, is presented in this paper operating in different frequency bands. Circuits functional in different operating conditions are considered in the paper to satisfy the requirement from low- to high-speed signals produced either from the wireless sensor or other signal source to be modulated on a …
Published in Journal of VLSI Design Tools and Technology · Vol. 2, Issue 1-2-3, 2012 · pp. 44–51 Read article
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High-speed CMOS ADCs Design
Abstract: This paper presents the design of high-speed subranging and flash analog to digital data converters (ADC) including the design of efficient operational amplifier to meet the performance requirements of these data converters for the specifications laid down targeted to the SCL 1.2 μm CMOS Foundry. The design starts from the specification of the circuit, its theoretical analysis for the parameter estimations of the transistors as well as the circuit’s design. …
Published in Journal of VLSI Design Tools and Technology · Vol. 2, Issue 1-2-3, 2012 · pp. 59–74 Read article
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Design and Analysis of Low-Power CMOS Inverter Chains for High-Speed Digital Circuits
Abstract: This report briefly explains the design process, structure, and evaluation of a CMOS inverter designed using a 45 nm technology process with a focus on its propagation delay and power consumption. Moreover, the CMOS inverter design will be created using the Cadence Virtuoso design environment, along with a post-layout analysis of the design. Performance evaluation of the designed circuit will be carried out through the execution of a transient analysis …
Published in Journal of VLSI Design Tools and Technology · Vol. 16, Issue 1, 2026 · pp. 40–57 Read article
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Investigation of Pass Transistor Logic and CMOS Logic Configuration Based D-Multiplexers
Abstract: Pass Transistor Logic (PTL) arrangement depicts a few rationale families utilized in the plan of incorporated circuits. It lessens the include of transistors utilized making distinctive rationale entryways, by killing excess transistors. The pass transistor is driven by an intermittent clock flag and goes about as an entrance change to ON (1) or OFF (0), contingent upon the information flag. The utilization of pass transistor rationale has brought about noteworthy …
Published in Journal of Microelectronics and Solid State Devices · Vol. 9, Issue 2, 2022 · pp. 1–8 Read article
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Hybrid CMOS-SET Inverter Design for Improved Performance using Tied Body-backgate Technique
Abstract: Single-electron transistors (SETs) are an attractive candidate for future functional elements in LSIs, because of their low-power consumption and small size. Integration of current CMOS technology with the emerging SET devices is an effective approach for improving density of integration in VLSI chips and ensuring ultra low power dissipation along with the advantages of CMOS technology like high gain, current drive, speed and matured fabrication technology. This paper investigates hybrid …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 1, 2015 · pp. 24–29 Read article
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Design of Active Filter using CMOS based IInd Generation Current Conveyor in Current Mode
Abstract: Traditional design techniques used in VLSI are in voltage mode, but these have drawbacks like low bandwidth, non-linearity and less gain. Current conveyors act similar to operational amplifiers but are advantageous over older VLSI design techniques because of high bandwidth-gain product, reduced power consumption etc. This paper consists of two parts: circuit diagram of current conveyor (which is a three terminal analog device) is discussed first and its working is …
Published in Journal of VLSI Design Tools and Technology · Vol. 9, Issue 1, 2019 · pp. 15–21 Read article
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Low Power 8-Bit Square Root Carry Select Adder Constructed By Using 8 Transistor Full Adder
Abstract: Carry select adder is the high speed adder which is designed to speed up arithmetic operations and to reduce the computation time. Carry select adder is used to perform fast arithmetic functions in data processing processors. Low power consumption, reduced area, reduced delay and increased speed are the most important features of the modern electronic system design. In this proposed work, 8 transistor full adder (8T full adder) is used …
Published in Journal of VLSI Design Tools and Technology · Vol. 4, Issue 1, 2014 · pp. 25–29 Read article
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Design of Low Power Folded Cascode Current Mirror CMOS OTA and Implementation of 2nd Order Gm-C IF Filter with Analysis of S-Parameter
Abstract: This paper deals with design and optimization of a cascode current mirror folded cascode operational transconductance amplifier is done in order to optimize MOS transistor sizing. The design of folded cascode OTA, which works for frequencies that lead to a base band circuit design for RF application, is based on transistor sizing methodology and Simulation results are performed using SPICE software and BSIM3V3 model for CMOS 0.18μm process, show that …
Published in Journal of VLSI Design Tools and Technology · Vol. 3, Issue 2, 2013 · pp. 12–23 Read article
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Low Power RF QPSK MODEM Design
Abstract: System-level simulation including design of CMOS circuits for radio frequency QPSK MODEM targeting applications in 2.45 GHz industrial, scientific and medical (ISM) band has been presented in this paper. Based on the QPSK architecture, the MODEM consists of an analog mixer using a voltage multiplier, a 90 °phase shifter, delay circuits, a voltage adder and a filter to detect the information. A code reuse subsystem block consisting of Chebyshev filter …
Published in Journal of VLSI Design Tools and Technology · Vol. 2, Issue 1-2-3, 2012 · pp. 75–86 Read article
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Design of Voltage Controlled Oscillator using GDPK 90nm CMOS Technology
Abstract: In the recent decade, there has been a major revolution in communication systems and devices. Many communication devices required a specific frequency which may range from a few Hz to several GHz by source of voltage. Voltage Control Oscillator (VCO) plays a major role in today’s modern communication system. Voltage Control Oscillator use as basic building block in communication circuits and major use in phase locked loops circuits. Due to …
Published in Journal of Electronic Design Technology · Vol. 13, Issue 1, 2022 · pp. 17–24 Read article
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Design and Performance Analysis of Multi-Standard CMOS LNA Using Switched Capacitor and MIM Capacitor in 180nm Technology
Abstract: Low noise amplifier (LNA) is terribly important block in designing broadband receivers for wireless broadband communications. Being the primary active element in receiver chain it creates larger demand for LNAs that are smaller, consume less power, and provide sufficient gain, low noise and high compact design. The projected LNA is extremely integrated with low noise figure having wide calibration range with improved RF power handling system and acquires less space …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 3, 2015 · pp. 37–44 Read article
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Reconfiguring CMOS Driver and Receiver Pair as Pseudo NMOS for Low-swing Signaling On-chip Interconnects
Abstract: The Low power bus architecture [9, 12, 13] consists of Driver, Receiver and Interconnects in between them inside the Chip. The Low power bus architecture [1] models are classified in to Symmetric and Asymmetric [7, 11, 14, 15] based on low voltage scaling technique and very simple design principles were utilized to construct driver, receiver and interconnects. The low power bus driver has the ability to switch from a low …
Published in Journal of VLSI Design Tools and Technology · Vol. 3, Issue 1, 2013 · pp. 20–27 Read article
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Design and Simulation of LNA in 90 nm CMOS Technology for Radio Receiver using the Cadence Simulation Tool
Abstract: Due to its successful operation in the 2.4 GHz frequency region, often known as the ISM (Industrial, Scientific, and Medical) band, RFICs play a vital role in communication systems. The major parts being used transceivers for frequency translation and amplification are LNA and Mixers. Different types of mixers and LNAs are employed, and different strategies are used to optimize them. In this paper an approach for design and simulation of …
Published in International Journal of Digital Communication and Analog Signals Read article
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Design and Simulation of Full Adder-Based CMOS 4-2 Compressor using CMOS XOR-XNOR Logic
Abstract: This study utilizes the recent development of CMOS transistors to construct an energy-efficient Full adder-based CMOS 4-2 compressor. The CMOS Exclusive-OR-Exclusive-NOR component and multiplexer used in the transmission logic of the novel CMOS compressor include eight transistors. The XOR-XNOR logic style is the most efficient and effective due to its speed and reduced power consumption. Utilizing an operational supply voltage of 0.7 V and 90nm CMOS technology, the Cadence Virtuoso …
Published in Recent Trends in Electronics Communication Systems · Vol. 12, Issue 3, 2025 · pp. 1–8 Read article
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Design of a 10-bit Segmented Current-Steering CMOS D/A Converter for High Speed Communication System
Abstract: In the present work, design of a 10-bit digital-to-analog (D/A) converter using current segmentation architecture in 0.35 µm double-poly, four-metal, CMOS process has been attempted. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.8 and 2.5 least significant bits (LSBs) respectively. For sampling frequency of 12-MSample/s, the spurious free dynamic range (SFDR) is better than 56 dB for signal up to Nyquist rate. The worst case power consumption …
Published in Journal of VLSI Design Tools and Technology · Vol. 2, Issue 1-2-3, 2012 · pp. 38–43 Read article
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Design and Implementation of Low Power Area Effective 2×4 Decoder for SARM Applications Using 16 nm Technology.
Abstract: This project involves analysis of Modified Mixed Logic Design abbreviated as MMLD which includes following design logics: Complementary Metal Oxide Semiconductor abbreviated to CMOS logic design, Gate Diffusion Input abbreviated as GDI technique, and Dual Value Logic called as DVL. Two logic styles are used in this paper study to reduce power dissipation and delay time which are fourteen 14-transistor and fifteen 15-transistor decoders. Every situation requires the use of …
Published in Journal of Semiconductor Devices and Circuits · Vol. 10, Issue 1, 2024 · pp. 24–36 Read article
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Design and Implementation of Low Power Priority Encoder
Abstract: Nowadays, low-power devices are widely used in VLSI design technology because they can reduce power consumption and power dissipation. To achieve this, various low-power techniques are utilized to minimize device power losses. This project focuses on analyzing the performance of priority encoders in different low-power technologies for Flash Type ADC. Moreover, the power consumption of these technologies is compared with the conventional CMOS design. Each of these techniques offers distinct …
Published in Journal of Microcontroller Engineering and Applications · Vol. 10, Issue 2, 2023 · pp. 1–14 Read article
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Design and Validation of Low Power High Speed area effective comparator using CMOS Technology
Abstract: The most fundamental arithmetic comparisons in a digital comparator involve comparing two numbers that are greater than, less than, or equal to each other. While doing enormous level arithmetic comparisons, a digital comparator needs more space, which results in higher power consumption and a delayed response. This can be solved by using N-bit comparator with two modules using 45GPDK CMOS Technology. An N-bit comparator can operate at extremely high speeds …
Published in Recent Trends in Electronics Communication Systems · Vol. 10, Issue 2, 2023 · pp. 20–29 Read article
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Design of Fault Tolerant Reversible Comparator
Abstract: Reversible circuits have proved its significance in the synthesis of circuits having their important role in nanotechnology, quantum computing, low power CMOS Design, cryptography and Bioinformatics. The Reversible Gates can be further made more beneficial if they prove themselves to be Fault Tolerant i.e. where errors can be detected and corrected at the same time. This Paper considers parity preserving technique for making Reversible circuits Fault Tolerant. Parity Preserving Gates …
Published in Journal of Semiconductor Devices and Circuits · Vol. 6, Issue 2, 2019 · pp. 13–17 Read article