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204 articles for “comparator circuit”
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A Simple, Compact, and Power-Efficient Current-Mode Decimal Adder Circuit
Abstract: A size and power efficient current-mode decimal adder is proposed in this paper. The proposed adder does not use binary coded decimal (BCD) number system for processing the decimal data like other decimal adders. Instead, it processes the decimal data as the actual decimal inputs. The proposed adder can be used as a decimal half adder as well as a decimal full adder. The adder is based on simple decimal …
Published in Journal of VLSI Design Tools and Technology · Vol. 4, Issue 2, 2014 · pp. 18–23 Read article
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A Comparative Analysis of Various Flipped Voltage Follower Cells
Abstract: Flipped voltage follower (FVF) cell is used for designing low-voltage/low-power analog circuits. It can operate with a single supply voltage, less than the sum of the threshold voltages of a PMOS and NMOS transistor. The three different configurations of the FVF cell namely conventional FVF, FVF using level shifter (FVFLS) and FVF using bulk driven technique (FVFBD) are presented. Various parameters such as input/output swing, gain, bandwidth and power dissipation …
Published in Journal of Microelectronics and Solid State Devices · Vol. 4, Issue 2, 2017 · pp. 1–8 Read article
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Simulation of Adder Circuit Using Reversible Gates in Verilog HDL
Abstract: The emerging field of quantum computing uses quantum logic gates. The reversibility of logic gates is an important aspect of quantum logic gates used in VLSI and quantum computing. Reversibility ensures that power consumption is minimized. This study explores the field of reversible logic and utilizes Peres gate to develop a full adder circuit that shows a significant reduction in power consumption in simulations performed in Xilinx Vivado. We have …
Published in Journal of VLSI Design Tools and Technology · Vol. 14, Issue 3, 2024 · pp. 32–38 Read article
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Power Analysis Comparison of Gated Diode Dram Cell Design on 32 nm Technology
Abstract: In this paper power consumption of Gated diode DRAM (Dynamic Random Access Memory) cells are carried out. This analysis is carried out on 32 nm scale. The DRAM cell used here are 3T1D and 2T1D DRAM cell. Static, total average and transient power for both types of cells are simulated in order to have a comparison of their performance on the same technology. A comparative study of different types of …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 1, 2015 · pp. 19–23 Read article
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Design of 10T SRAM Cell for Low Power and High Speed Applications
Abstract: AbstractThis paper presents techniques for designing a low-power and higher read speed Static Random Access Memory (SRAM) cell. The cell achieves low power dissipation due to Virtual Ground (VGND) scheme and provides higher read performance due to Forward Body Biasing (FBB). Design metrics of the proposed SRAM cell was studied and compared with that of CON 6T, CON D10T, TG 8T, 9T, and ST-10T SRAM cells. It was observed that …
Published in Journal of Electronic Design Technology · Vol. 8, Issue 2, 2017 · pp. 16–27 Read article
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Analysis of Signal Delay in Carbon Nano Tube based Interconnects at 32 nm Technology Node
Abstract: AbstractIn the present world demand for portable devices and high speed processor is rising which brings out a challenging issue of scaling for designers. In this paper, we have presented the effect of copper and CNT based interconnects for different length at 32 nm technology node. The performance of both types of interconnects are analyzed and compared in form of propagation delay. Propagation delay in interconnects between the elements is …
Published in Journal of Microelectronics and Solid State Devices · Vol. 5, Issue 1, 2018 · pp. 20–26 Read article
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Low Power and High Speed Techniques for Sequential Circuits
Abstract: This paper proposes techniques like MT-CMOS, power gating, dual stack, Galeor and Lector to reduce the leakage power. A D-Flip Flop has been designed using these techniques and power dissipation is calculated and is compared with general CMOS logic of D Flip Flop. Simulation results show the validity of the proposed techniques is effective to save power dissipation and to increase the speed of operation of the circuits to a …
Published in Journal of Power Electronics and Power Systems · Vol. 4, Issue 3, 2014 · pp. 41–45 Read article
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Reconfiguring CMOS Driver and Receiver Pair as Pseudo NMOS for Low-swing Signaling On-chip Interconnects
Abstract: The Low power bus architecture [9, 12, 13] consists of Driver, Receiver and Interconnects in between them inside the Chip. The Low power bus architecture [1] models are classified in to Symmetric and Asymmetric [7, 11, 14, 15] based on low voltage scaling technique and very simple design principles were utilized to construct driver, receiver and interconnects. The low power bus driver has the ability to switch from a low …
Published in Journal of VLSI Design Tools and Technology · Vol. 3, Issue 1, 2013 · pp. 20–27 Read article
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Design and Simulation of Low Power Allow Area High Speed Carry Save Adder using CMOS 16 nm Technology.
Abstract: In this article, we propose a novel 1-bit hybrid full adder circuit that is implemented using eighteen transistors. Simulations are done using the Mentor Graphics Tool 16nm technologies. The performances are evaluated based on their speed, average power consumption, and power-delay product. The essential components of arithmetic units including compressors, comparators, parity checkers, etc. are full adders. Thus, raising the performance of the entire adder will raise the system's performance. …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 1, Issue 2, 2023 · pp. 17–28 Read article
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Analysis of Six-Pulse Bridge Circuits Including Zener and Semiconductor Diodes – Part Two
Abstract: The present study offers a generic method for simulating and modelling six-pulse rectifier bridge circuits in the time domain. These circuits can include Zener and/or semi-conductor type diodes or even a mixture of them. The governing system of simultaneous algebraic and differential equations are listed and solved numerically using a computer code written in Mathematica. The flexibly written program can handle voltage sources of any time waveform, frequency or internal …
Published in Journal of VLSI Design Tools and Technology · Vol. 12, Issue 2, 2022 · pp. 13–21 Read article
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An Optimized 32 bit Carry Select Adder Using Modified BEC
Abstract: AbstractAdders play a major role in addition of numbers, multiplications and other advanced processors’ design. Among the conventional adder structures, carry select adder is known to be fastest adder. This adder circuit is used for the design of high speed processors. The CSLA adder architecture is such that it is of less power dissipation, area efficient and high speed. CSLA circuit for 8, 16, 32 bits is designed without multiplexer …
Published in Journal of Semiconductor Devices and Circuits · Vol. 5, Issue 2, 2018 · pp. 27–32 Read article
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Design of Low Noise Transimpedance Amplifier using Multiple Feedback filter Topology
Abstract: This study presents the highly linear and low noise transimpedance amplifier (TIA) based on CMOS inverter as an amplifier within multiple feedback (MPFB) filter topology. Absence of complex analog circuitry and compatibility with widespread digital CMOS processes highlight this TIA topology asthe best choice in signal conditioning chains approaching analog-to-digital converters (ADCs). Special attention has been given to the TIA stability and compensation networks. Using dedicated low-dropout (LDO) regulator, the …
Published in Journal of Electronic Design Technology · Vol. 13, Issue 1, 2022 · pp. 25–30 Read article
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Reusable FM0/Manchester Encoding Using QCA
Abstract: Dedicated short range communication (DSRC) is an important technique which is used for transmission of high speed data in communication based safety applications. For signal reliability and dc balance, it uses either Manchester or FM0 coding technique. Code word structure for both FM0 and Manchester are different, which makes limitation on the hardware potential of DSRC system So, SOLS technique is used to conquer this limitation which combines the hardware …
Published in Journal of VLSI Design Tools and Technology · Vol. 9, Issue 1, 2019 · pp. 51–59 Read article
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Classification and Comparison of Routing Protocols in Wireless Sensor Networks
Abstract: Recent developments and the overlap of multiple technologies, including distributed signal processing, ad-hoc network routing protocols, embedded systems, integrated circuits, micro electro-mechanical systems, microprocessor hardware, and nanotechnology, have rendered the idea of Wireless Sensor Networks (WSNs) possible. Sensor network nodes are finite with regard to energy, processing capability, and communication bandwidth. Yet, since they can vary with respect to the application and network structure, the routing protocols have received the …
Published in International Journal of Wireless Security and Networks · Vol. 3, Issue 2, 2025 · pp. 35–44 Read article
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Design, Verification and Circuit Level Implementation of a Ballistic MOSFET
Abstract: A drain current expression is obtained for a nanoscale ballistic MOSFET within the framework of Landauer-Buttiker formalism considering intrinsic silicon channel at low temperature. The model drain current is compared with the numerical simulations of near ballistic nanoMOSFET structure. There is a reasonable agreement between the model and the numerical simulation results. This demonstrates the remarkably low value of the subthreshold slope of ballistic nanoMOSFET. Further, the design structure is …
Published in Journal of VLSI Design Tools and Technology · Vol. 8, Issue 3, 2018 · pp. 15–22 Read article
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Design and Implementation of Array for Scaling Power and Area in 4t SRAM Cell
Abstract: In this article in order to reduce the power and area of the Static Random-Access Memory (SRAM) array while maintaining the competitive performance. By using the CMOS technology, the design structure is made to for desired configuration of SRAM array by utilizing the SRAM cell and six-transistor (6T), In order to reduce the number of switches for enhancing performance working with the deep submicron of values 130nm, 90nm and 65nm …
Published in Journal of Semiconductor Devices and Circuits · Vol. 9, Issue 1, 2022 · pp. 29–33 Read article
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A Novel Conflict-Free Efficient Memory-Based Real FFT Processor using UTB
Abstract: AbstractWe present “A Novel Conflict-Free Efficient Memory-Based Real Fast Fourier Transform (RFFT) using Urdhva Tiryagbhayam Butterfly”. In this paper different FFT lengths for address schemes are integrated that supports FFT processing which are used in diverse systems such as telecommunications. Address methods for various FFT lengths are coordinated in this paper to help FFT processing for different frameworks like broadcast communications. The memory bank and address can be produced by …
Published in Journal of VLSI Design Tools and Technology · Vol. 9, Issue 3, 2019 · pp. 1–11 Read article
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CMOS-Based Process-Scalable Analog Circuits for Machine Learning: A Comprehensive Review and Future Directions.
Abstract: Analog computing techniques are gaining attention for machine learning (ML) applications due to their ability to reduce computational complexity. Continuous operations such as addition and subtraction offer a simpler and more efficient approach compared to probabilistic product decoding, which can be sensitive to noise and inconsistent measurements. This paper presents a simulated VLSI implementation of a broadcast edge connection, independent of the MOS component model, along with experimental results. The …
Published in Journal of VLSI Design Tools and Technology · Vol. 15, Issue 1, 2025 · pp. 8–17 Read article
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Design of Universal Coil for Medium Voltage Switchgear
Abstract: In the market, currently multiple ratings of D.C. voltages are available for the auxiliary supply of medium voltage switchgear. There is a wide range of D.C. supplies used in the medium voltage segment like 24 V, 30 V, 48 V, 60 V, 110 V, 125 V and 220 V. Normally the closing coil and tripping coil of a circuit breaker are designed for a specific auxiliary supply voltage which leads …
Published in Recent Trends in Sensor Research & Technology · Vol. 4, Issue 2, 2017 · pp. 26–30 Read article
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Advanced Liquid Crystal Polymer Substrate for Flexible Antenna Design
Abstract: A type of thermoplastic polymers known as liquid crystal polymers (LCPs) is frequently used to package millimeter (mm)-wave, microwave, and radio frequency (RF) integrated circuits that operate at frequencies as high as 60GHz. LCPs are of prospective relevance as packaging material for advanced circuits at mm-wave frequencies due to their appealing electrical, thermal, and mechanical qualities and comparatively low cost. Flexible and conformal antennas are made possible by LCP's exceptional …
Published in Journal of Polymer & Composites · Vol. 14, Issue 2, 2026 · pp. 233–245 Read article