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136 articles for “CMOS Circuit”
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Investigation of Pass Transistor Logic and CMOS Logic Configuration Based D-Multiplexers
Abstract: Pass Transistor Logic (PTL) arrangement depicts a few rationale families utilized in the plan of incorporated circuits. It lessens the include of transistors utilized making distinctive rationale entryways, by killing excess transistors. The pass transistor is driven by an intermittent clock flag and goes about as an entrance change to ON (1) or OFF (0), contingent upon the information flag. The utilization of pass transistor rationale has brought about noteworthy …
Published in Journal of Microelectronics and Solid State Devices · Vol. 9, Issue 2, 2022 · pp. 1–8 Read article
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A Comparative Analysis of Various Flipped Voltage Follower Cells
Abstract: Flipped voltage follower (FVF) cell is used for designing low-voltage/low-power analog circuits. It can operate with a single supply voltage, less than the sum of the threshold voltages of a PMOS and NMOS transistor. The three different configurations of the FVF cell namely conventional FVF, FVF using level shifter (FVFLS) and FVF using bulk driven technique (FVFBD) are presented. Various parameters such as input/output swing, gain, bandwidth and power dissipation …
Published in Journal of Microelectronics and Solid State Devices · Vol. 4, Issue 2, 2017 · pp. 1–8 Read article
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Automatic Switch cum Fuse IC for Low Voltage, Low Power, High Performance Current Conveyors
Abstract: The paper focuses on the analysis of switch cum fuse IC in signal processing. In signal processing it is proposedto prevent the damage of main IC from the external electrical fluctuations which are common in -these days. Theproposed FUSE IC is also able to act as fuse for many times for main IC so that it can prevent the damage. It’slike the work of MCB but a step ahead that …
Published in Journal of VLSI Design Tools and Technology · Vol. 1, Issue 1-2-3, 2011 · pp. 21–25 Read article
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Implementation of a 4-Bit Synchronous Counter in SkyWater 130 nm CMOS Technology Using Open-Source EDA Tools
Abstract: As semiconductor technology continues to scale down, the physical layout of integrated circuits has become increasingly critical in determining performance, power consumption, and area efficiency. This paper presents the complete physical design implementation of a 4-bit counter, from Register Transfer Level (RTL) to GDSII, using the SkyWater 130 nm open-source Process Design Kit (PDK) and the OpenLane automated physical design flow. Functional verification of the RTL design was initially performed …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 4, Issue 2, 2026 Read article
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Design and Implementation of Low-power SPI Shift Register
Abstract: SPI stands for serial peripheral interface which is used for serial, synchronous and full duplex communication of data between master and slave devices. Master devices can be Microprocessors or Microcontrollers; and slaves are the Peripheral devices interfaced with them. The main internal component for architecture of master/slave block is shift register which defines its operation. But as the size of the shift register increases, power is utilized to a greater …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 1, Issue 1, 2023 · pp. 1–15 Read article
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Design and Implementation of Low Noise Power Low and High Speed Three Stage Comparator Using 16nm Technology
Abstract: To meet the demands of quicker operation and reduced noise levels, this study proposes a new CMOS Three-based comparator version. Efficiency may be significantly improved by comparing the suggested model to existing ones. This is so because the suggested comparator would improve the efficiency of the current amplifier design. The suggested model drives the input pairs of the regenerator and the amplified stage, making for a quicker comparator. The structure …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 1, Issue 2, 2023 · pp. 10–16 Read article
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Design and Analysis of Bootstrap Sample and Hold Circuit
Abstract: This paper describes the design and implementation of open-loop sample and hold-circuit using bootstrap technique, which can be used as front end sampling circuit for high-speed analog-to-digital converters. Different design criteria, viz., speed, power, resolution, linearity, noise and harmonic analysis have been dealt with. Both theoretical analysis and simulation results are carried out. The bootstrap circuit is designed and then compared in a 0.18 and 0.35 μm CMOS process. It …
Published in Journal of Electronic Design Technology · Vol. 5, Issue 3, 2014 · pp. 7–14 Read article
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Review Paper: Low Power SRAM Cell using FinFET Technology
Abstract: To make portable battery operated devices more efficient with low leakage current has become a major challenge with the technology scaling. As the technology is scaling, the bulk MOSFET faces various challenges which lead to increased leakage current. FinFET is the most encouraging substitute to bulk CMOS, because of the reduced short channel effect. The FinFET device based circuits portrays advantages with its better control over the device channel and …
Published in Journal of VLSI Design Tools and Technology · Vol. 8, Issue 1, 2018 · pp. 43–47 Read article
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Design of Low Power Folded Cascode Current Mirror CMOS OTA and Implementation of 2nd Order Gm-C IF Filter with Analysis of S-Parameter
Abstract: This paper deals with design and optimization of a cascode current mirror folded cascode operational transconductance amplifier is done in order to optimize MOS transistor sizing. The design of folded cascode OTA, which works for frequencies that lead to a base band circuit design for RF application, is based on transistor sizing methodology and Simulation results are performed using SPICE software and BSIM3V3 model for CMOS 0.18μm process, show that …
Published in Journal of VLSI Design Tools and Technology · Vol. 3, Issue 2, 2013 · pp. 12–23 Read article
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Single Bit Low-Power High-Speed Full Adder
Abstract: This paper presents a high-speed low-power full adder cells that lead to have a reduced power-delay product (PDP). A comparison against other full-adder structure as having low PDP, in terms of speed, power consumption and area of cells is carried out. This paper contains, a hybrid 1-bit full adder design employing both complementary metal-oxide semiconductor (CMOS) and transmission gate logic styles. First implemented was the design for 1 bit then …
Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 3, 2017 · pp. 55–60 Read article
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Single Bit Low-Power High-Speed Full Adder
Abstract: This paper presents a high-speed low-power full adder cells that lead to have a reduced power-delay product (PDP). A comparison against other full-adder structure as having low PDP, in terms of speed, power consumption and area of cells is carried out. This paper contains, a hybrid 1-bit full adder design employing both complementary metal-oxide semiconductor (CMOS) and transmission gate logic styles. First implemented was the design for 1 bit then …
Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 2, 2017 · pp. 55–60 Read article
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Current Controlled Oscillator Using FinFET
Abstract: A current-controlled oscillator using 18 nm FinFET technology is proposed in this study which consists of a Current Controlled Differential Difference Current Conveyor (CCDDCC) block to control the current. FinFET technology has better scalability and lower leakage current compared to traditional CMOS, which allows it to surpass the obstacles faced by CMOS-based oscillators. The suggested oscillator is suitable for electronic applications such as Phase-Locked Loop (PLL) systems, radio frequency (RF) …
Published in Journal of Semiconductor Devices and Circuits · Vol. 12, Issue 3, 2025 · pp. 17–28 Read article
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Automatic Gain Control Amplifier for Analog Front End in Biomedical Applications
Abstract: This paper presents the design review of feed-forward automatic gain control (AGC) amplifier to be used in analog front end of biomedical applications such as hearing aid. To make system low-power, the design of each block is optimized and all elements are realized using MOS. The whole design is simulated in LT spice IV using 0.18 µm CMOS technology and the results are presented. Keywords: Automatic gain control (AGC), biomedical …
Published in Research and Reviews : A Journal of Medical Science and Technology · Vol. 5, Issue 3, 2016 · pp. 22–26 Read article
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A Differentiator Based on Second Generation Current Controlled Conveyor
Abstract: A new second generation current controlled conveyor (CCCII) with programmable gain at output terminal ‘Z’ is presented in this paper. The inherent advantages of the proposed circuits are low supply voltage requirement of ±0.85 V, small input parasitic resistance in the range of 29.12 Ω–297.71 Ω for a current range of 10 µA–300 µA, low power dissipation of 79.39 µw and low DC current error of 0.068%. The proposed CCCII …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 1, 2016 · pp. 89–95 Read article
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A study on CMOS Operational Amplifier in Sensor Development
Abstract: CMOS operational amplifiers (op-amps) have emerged as pivotal components in modern sensor development, enabling the amplification and conditioning of weak signals with high precision and efficiency. Their inherent advantages low power consumption, compact size, and seamless integration with digital circuits make them ideal for advancing miniaturized, battery-powered sensor systems in fields ranging from biomedical devices to IoT networks. By delivering precision, power efficiency, and integration, CMOS op-amps are not just …
Published in Journal of VLSI Design Tools and Technology · Vol. 16, Issue 1, 2026 · pp. 01–07 Read article
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Implementation of Sub Parts of SAR ADC
Abstract: This paper describes the implementation of different sub parts of SAR ADC using a 180 nm CMOS technology in Mentor Graphics Tool. There are mainly four blocks in the SAR ADC. They are sample and hold, dynamic latch comparator, SAR logic and DAC logic. The simulation results show the transient analysis waveforms of different blocks of SAR ADC. Here to reduce power consumption dynamic latch comparator is used. Here the …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 3, 2015 · pp. 139–147 Read article
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Characterization of High Speed Phase Frequency Detector Circuit
Abstract: In this paper the performance of high speed phase frequency detector (PFD) is analysed. A high-speed PFD reduces the power consumption of traditional PFD to 0.423 nW at 1 GHz clock frequency and dead zone to 2 ps. It is suitable for low power applications. A PFD uses only 18 transistors. This PFD operates up to 1 GHz at 1.2 V supply voltage. The proposed architecture of the PFD has …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 1, 2015 · pp. 51–58 Read article
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Spintronic Logic Device Modeling and Energy Optimization for Beyond-CMOS Computing Systems
Abstract: The continuous scaling limitations of conventional CMOS technology have accelerated the exploration of alternative computing paradigms for next-generation low-power and high-performance systems. Spintronic logic devices have emerged as a promising solution due to their non-volatility, ultra-low switching energy, high integration density, and compatibility with beyond-CMOS architectures. This research presents a comprehensive modeling and energy optimization framework for spintronic logic devices applied in beyond- CMOS computing systems. The proposed work investigates …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 4, Issue 1, 2026 Read article
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Short Review on Fluid Mechanics with the Domain of Nanotechnology for Applications in Nuclear-Reactors
Abstract: In this work, a brief review on microfluidic flow is provided. Also, the brief ideas on very large scale integration (VLSI) circuits are provided. A single polymethylmethacrylate (PMMA) based gradual expansion microchannel is fabricated by the maskless lithography, hot embossing lithography and direct bonding technique. Surface-driven microfluidic flow of dyed water is recorded in the fabricated device using a CMOS camera catching 25 frames per second with a corresponding time-scale …
Published in Nano Trends – A Journal of Nano Technology & Its Applications · Vol. 23, Issue 2, 2021 · pp. 45–50 Read article
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A Study on Polymer-Based FinFET Applications and Logic Circuit Implementation with FinFET
Abstract: Nano devices play a crucial role in the semiconductor industry and can work as the solution for the problems like scaling of MOSFET. The FinFET can serve as the substitute of bulk CMOS in nanoscale. It mainly consists of two gate terminals which can be either shorted or kept independent.The shorted gate (SG-FinFET) configuration provides higher Ion and Ioff whereas the Independent Gate (IG-FinFET) configuration reduces the transistor count and …
Published in Journal of Polymer & Composites · Vol. 13, Issue 1, 2025 · pp. 312–340 Read article