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156 articles for “gating design”
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VLSI Based Traffic Light Controller
Abstract: This study details the development and realization of an advanced traffic light control system utilizing VHDL (Very High-Speed Integrated Circuit Hardware Description Language) in conjunction with FPGA (Field Programmable Gate Array) technology. The system is designed to regulate a four-way intersection, with one primary high-traffic road intersecting with a less congested side road. To enhance traffic efficiency and minimize idle times, the model incorporates intelligent features such as a vehicle …
Published in Journal of VLSI Design Tools and Technology · Vol. 15, Issue 2, 2025 · pp. 40–47 Read article
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FDTD-based Time Domain Analysis of CMOS Gate Driven Interconnects
Abstract: Accurate time domain analysis of CMOS gate driven interconnects is important for the design and analysis of high performance VLSI systems. Conventionally, CMOS driver is approximated as a constant resistance instead of non-linear and time-varying MOS resistance, which causes inaccurate modeling of CMOS driver. This paper presents a new method for FDTD-based transient analysis of CMOS gate driven interconnect line using a generalized model. The generalized model of CMOS inverter …
Published in Journal of Electronic Design Technology · Vol. 5, Issue 1, 2014 · pp. 16–21 Read article
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Variations of Source Current in the Double-Heterojunction HEMTs
Abstract: AbstractIn this report, we have studied the variations in source current with respect to drain voltage corresponding to the double heterojunction (DH) high electron mobility transistors (HEMTs). Also, the effects of gate voltage and aluminium mole fractions on source current are studied. In this work, the highest source current achieved is 3.3 mA. This work may be useful to design many nanoelectronic HEMTs.Keywords: Source current, drain voltage, gate voltage, mole …
Published in Journal of Semiconductor Devices and Circuits · Vol. 3, Issue 3, 2016 · pp. 19–24 Read article
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Simulation and Analysis to Reduce the Shrinkage Defect in Sand Casting for the Rotor: A Review
Abstract: Casting is a process in which the metal is melted and poured into mold and allows it to solidify to get desired shape. Objective of investigation is to review on simulation and analysis to reduce the shrinkage defect in sand casting. In ductile iron casting, shrinkage defect is common. It is generally seen at the last solidifying area of casting. Other parameters like getting system, feeder, metallurgy of material, part …
Published in Journal of Production Research & Management · Vol. 7, Issue 3, 2017 · pp. 23–26 Read article
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Comparative Study of Symmetric and Asymmetric Oxide Double Gate Junction less FET
Abstract: we carry out the performance of symmetric oxide (HfO2+HfO2) and asymmetric oxide (SiO2+HfO2) n-type junction less field-effect transistor (JLFET) based on two- dimensional Poisson equation. This study is accomplished by simulating a symmetric and asymmetric double gate JLFET on Sentaurus, Technology Computer Aided Design (TCAD) simulator for Silicon (Si) material at room temperature and varying temperature in between 300-360 k. Based on device simulation we find that the asymmetric oxide …
Published in Journal of Semiconductor Devices and Circuits Read article
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Simulation of Adder Circuit Using Reversible Gates in Verilog HDL
Abstract: The emerging field of quantum computing uses quantum logic gates. The reversibility of logic gates is an important aspect of quantum logic gates used in VLSI and quantum computing. Reversibility ensures that power consumption is minimized. This study explores the field of reversible logic and utilizes Peres gate to develop a full adder circuit that shows a significant reduction in power consumption in simulations performed in Xilinx Vivado. We have …
Published in Journal of VLSI Design Tools and Technology · Vol. 14, Issue 3, 2024 · pp. 32–38 Read article
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Comparative Study of Symmetric and Asymmetric Oxide Double Gate Junction less FET
Abstract: We carry out the performance of symmetric oxide (HfO2+HfO2) and asymmetric oxide (SiO2+HfO2) n-type junction less field-effect transistor (JLFET) based on two- dimensional Poisson equation. This study is accomplished by simulating a symmetric and asymmetric double gate JLFET on Sentaurus, Technology Computer Aided Design (TCAD) simulator for Silicon (Si) material at room temperature and varying temperature in between 300-360 k.Based on device simulation we find that the asymmetric oxide shows …
Published in Journal of Semiconductor Devices and Circuits · Vol. 8, Issue 2, 2021 · pp. 14–20 Read article
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Effect of Aluminium Nitride Layer on the Electrical Performance of Microelectronic HEMTs
Abstract: AbstractIn this simulation work, a series of simulation outputs are reported related to the AlGaN/GaN single-heterojunction high electron mobility transistors (HEMTs). The effect of aluminium nitride nucleation layer on the drain characteristics is significant in single-heterojunction AlGaN/GaN HEMTs. The effects of drain voltage and gate voltage on the drain current are studied in the designed and simulated device structures. This simulation work may be a useful prediction to fabricate the …
Published in Journal of Microelectronics and Solid State Devices · Vol. 4, Issue 3, 2017 · pp. 9–12 Read article
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Optimized AES Implementation on Leon3
Abstract: This paper presents implementation of AES (Advanced Encryption Standard) on LEON3 which is a soft-core processor. We have used the AMBA (Advanced Microcontroller Bus Architecture) bus for interfacing our AES IP (Intellectual Property) core with Leon3 processor. AMBA bus is an in built open source bus which comes along with Leon3 processor. We have mainly analyzed parameters such as throughput, slice utilization and compared our model based with previous work. …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 1, 2015 · pp. 30–33 Read article
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Design of High-Speed and Low-Power Carry Skip Adder
Abstract: In this brief, we present a high speed and lower power consumption carry skip adder (CSKA) architecture compared with the conventional one. The increment of speed is attained by implementing concatenation and incrementation strategy to improve the efficiency of the conventional CSKA (Conv-CSKA) architecture. Instead of make use of multiplexer logic, the proposed architecture makes use of AND-OR-Invert (AOI) and OR-AND-Invert (OAI) combination gates for the carry skip logic. The …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 3, 2016 · pp. 35–44 Read article
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Evaluating the Performance of a Smart VCR System Using Python for Data Analysis Based on IoT
Abstract: Commercial buildings use a significant amount of electricity, with around 60% to 80% being attributed to the HVAC system. Implementing IoT and smart sensors can help reduce this consumption by 10% to 30%. To lower the electricity usage of air conditioners, a study has proposed an IoT-based smart VCR system with sensors, meters, gateway, and cloud computing modules. This system is designed to collect data and regulate the VCR system …
Published in Journal of Control & Instrumentation · Vol. 15, Issue 2, 2024 · pp. 7–23 Read article
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The Role of Majority Functions in Enhancing Full Subtractor Performance in High-Density Logic Circuits
Abstract: In the present trend of very large-scale integration (VLSI) technology, implementing a Boolean function with the fewest number of gates (logic) has always been important. Low power design strategies now provide much more benefits than in the past. Performance, affordability, and dependability may be key issues in this area of technology design. Power dissipation is now recognized as a crucial component in the development of competitive market areas such wireless …
Published in Journal of Semiconductor Devices and Circuits · Vol. 11, Issue 2, 2024 Read article
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Investigation and Dependency Analysis of Silicon Film Thickness on Performance of Surrounding Gate MOSFET at Subthreshold Regime
Abstract: The characteristics of cylindrical gate all around MOSFET have been studied in terms of the dependence of various device performance metrics on silicon film thickness (Tsi). In this work, the effect of silicon film thickness on numerous performance metrics like threshold voltage (Vt), On current (Ion), subthreshold leakage current (Ioff), On-Off current ratio (Ion/Ioff) and DIBL of cylindrical GAA are comprehensively evaluated and analysed. It has been observed that cylindrical …
Published in Journal of VLSI Design Tools and Technology · Vol. 8, Issue 2, 2018 · pp. 49–54 Read article
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Swing Restored Low Power and Area Efficient 8-bit Arithmetic Logic Unit Using Modified Gate Diffusion Input Technique
Abstract: AbstractThe arithmetic logic unit (ALU) is one of the most fundamental operational units in any processor. The ALU is the heart of any system or any processor and the core component of the central processing unit because mainly all the fundamental operations are performed by the help of ALU only. So, it can be defined as the combinational unit that is used to perform its logical and arithmetic units. The …
Published in Journal of Microcontroller Engineering and Applications · Vol. 5, Issue 2, 2018 · pp. 19–29 Read article
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Optimization of a Digital Adder Design Using MOSFET and FinFET Technology
Abstract: AbstractIn this study, a very low power high speed Adder is presented by using short gate mode technique and voltage scaling system for FinFET. MOSFET and FinFET technique is used on 32 nm by adders which compare delay and average power. Parametric study of fins vs. power is also performed in the study. Synopsys HSPICE software is used for obtaining the simulation results. Simulation results show that low power is …
Published in Journal of Electronic Design Technology · Vol. 9, Issue 2, 2018 · pp. 30–33 Read article
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Reduce Timing in Physical Design
Abstract: AbstractThe physical design flow consists of producing a production worthily from a gate level net list subject set of constraints. Here, focuses on the reduce the timing from floor plan to routing stage. Because performance of a chip depend on the timing. Mainly in routing stage manually adding the buffers and upsizing the drive strength in violating the time paths. It also surveys some physical design flows. The outlines a …
Published in Journal of Microelectronics and Solid State Devices · Vol. 6, Issue 3, 2019 · pp. 28–36 Read article
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Power-delay Product Optimal Design of Sequential Circuits Using Carbon Nanotubes
Abstract: This paper presents a power-aware high-performance design of ternary combinational and sequential circuits based on carbon nanotube field effect transistor (CNFET) using ternary logic. Carbon nanotube based field effect transistor (CNFET) are being studied extensively as a possible and promising choice for nanoscale integration and as successor to complementary metal oxide semiconductor (CMOS) devices. Ternary logic circuit has attracted substantial interest due to its simplicity, energy efficiency, and reduced interconnect …
Published in Journal of VLSI Design Tools and Technology · Vol. 3, Issue 3, 2013 Read article
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Design of an Automatic Device Controller Based on Temperature Sensing by Using Verilog HDL Targeting an FPGA
Abstract: To get a single controller that is capable to produce some control signal depending on sensing temperature is getting popularities for industrial and home applications. In this paper uses an LM34 Precision Fahrenheit Temperature Sensor IC and an ADC0820 8-Bit, high-speed, µP-compatible flash A/D converter IC in order to design and implement the mentioned controller onto a SPARTANTM-II Field Programmable Gate Array (FPGA) by using DigilentTM Pegasus SPARTAN-II FPGA Board, …
Published in Journal of Control & Instrumentation · Vol. 3, Issue 1-3, 2012 · pp. 6–16 Read article
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Design and Implementation of Low-power SPI Shift Register
Abstract: SPI stands for serial peripheral interface which is used for serial, synchronous and full duplex communication of data between master and slave devices. Master devices can be Microprocessors or Microcontrollers; and slaves are the Peripheral devices interfaced with them. The main internal component for architecture of master/slave block is shift register which defines its operation. But as the size of the shift register increases, power is utilized to a greater …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 1, Issue 1, 2023 · pp. 1–15 Read article
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FPGA Implementation of Variable Step Size Adaptive Filters for Signal De-noising
Abstract: This paper presents the design and implementation of a variable step size 40 order adaptive filter for de-noising acoustic signals. Four different adaptive filters (LMS, Sign-Data, Sign-Error and Sign-Sign) were designed using three different structures, viz., direct form, transposed and the proposed structure and their de-nosing performance was compared. Further, the filters were implemented on three different Field programmable gate arrays (FPGAs), viz., Spartan 6, Virtex 6 and Viretx 7 …
Published in Journal of Semiconductor Devices and Circuits · Vol. 1, Issue 3, 2014 · pp. 7–19 Read article