STM Journals Peer-reviewed research from Consortium e-Learning Network

Journal of Semiconductor Devices and Circuits

FPGA Implementation of Variable Step Size Adaptive Filters for Signal De-noising

  1. Ravi Kumar
  2. Aditya Bali

Abstract

This paper presents the design and implementation of a variable step size 40 order adaptive filter for de-noising acoustic signals. Four different adaptive filters (LMS, Sign-Data, Sign-Error and Sign-Sign) were designed using three different structures, viz., direct form, transposed and the proposed structure and their de-nosing performance was compared. Further, the filters were implemented on three different Field programmable gate arrays (FPGAs), viz., Spartan 6, Virtex 6 and Viretx 7 which are designed on three device families and their speed , power and area utilization are computed. It was observed that due to significant reduction in the critical path, the proposed structure uses less number of slice LUTs resulting in a reduction in silicon area without incurring any significant overhead in terms of power or delay.
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