STM Journals Peer-reviewed research from Consortium e-Learning Network

Journal of Semiconductor Devices and Circuits Article Open Access

Comparative Study of Symmetric and Asymmetric Oxide Double Gate Junction less FET

  1. Kunal Kumar National Cheng Kung University Tainan

Abstract

we carry out the performance of symmetric oxide (HfO2+HfO2) and asymmetric oxide (SiO2+HfO2) n-type junction less field-effect transistor (JLFET) based on two- dimensional Poisson equation. This study is accomplished by simulating a symmetric and asymmetric double gate JLFET on Sentaurus, Technology Computer Aided Design (TCAD) simulator for Silicon (Si) material at room temperature and varying temperature in between 300-360 k. Based on device simulation we find that the asymmetric oxide shows preferable performance in terms of ON-state current (ION), subthreshold swing(SS), the ION/IOFF ratios (~107 ) and the equivalent oxide thickness (EOT) compared to symmetric devices and also asymmetric oxide technology enhances the performance and reduces the power consumptions.

Keywords

References (15)

  1. Lee CW, Borne A, Ferain I, Afzalian A, Yan R, Dehdashti Akhavan N, et al. High-Temperature Performance of Silicon Junctionless MOSFETs. IEEE Transactions on Electron Devices. 2010;57(3):620-625. doi:10.1109/ted.2009.2039093
  2. Li X, Han W, Ma L, Wang H, Zhang Y, Yang F. Low-Temperature Quantum Transport Characteristics in Single n-Channel Junctionless Nanowire Transistors. IEEE Electron Device Letters. 2013;34(5):581-583. doi:10.1109/led.2013.2250898
  3. Kumar K, Hsieh YF, Liao JH, Kao KH, Wang YH. Significance of Multivalley and Nonparabolic Band Structure for GeSn TFET Simulation. IEEE Transactions on Electron Devices. 2018;65(10):4709-4715. doi:10.1109/ted.2018.2864544
  4. Sahay S, Kumar MJ. Realizing Efficient Volume Depletion in SOI Junctionless FETs. IEEE Journal of the Electron Devices Society. 2016;4(3):110-115. doi:10.1109/jeds.2016.2532965
  5. Colinge JP. Junctionless transistors. 2012 IEEE International Meeting for Future of Electron Devices, Kansai. 2012:1-2. doi:10.1109/imfedk.2012.6218561
  6. Berthome M, Barraud S, Ionescu A, Ernst T. Physically-based, multi-architecture, analytical model for junctionless transistors. Ulis 2011 Ultimate Integration on Silicon. 2011:1-4. doi:10.1109/ulis.2011.5757988
  7. Sahu, S.R.; Agrawal, R.S.; Balwani, S.M. Review of Junctionless transistor using CMOS technology and MOSFETs. Int. J. Comput. Appl. 2012, 2012, 8–11
  8. J.P. Colinge, A. Kranti, R. Yan, C.W. Lee, I. Ferain, R. Yu, N. Dehdashti Akhavan, P. Razavi, Junctionless Nanowire Transistor (JNT): Properties and design guidelines, Solid-State Electronics, Volumes 65–66, 2011, Pages 33-37, ISSN 0038-1101.
  9. Ang, J.; Wan, Q.; Zhang, Q. Transparent junctionless electric-double-layer transistors gated by a reinforced chitosan-based biopolymer electrolyte. IEEE Trans. Electron. Devices 2013, 60, 1951–1957.
  10. Rios R, Cappellani A, Armstrong M, Budrevich A, Gomez H, Pai R, et al. Comparison of Junctionless and Conventional Trigate Transistors With $L_{g}$ Down to 26 nm. IEEE Electron Device Letters. 2011;32(9):1170-1172. doi:10.1109/led.2011.2158978
  11. Robertson, John. "High dielectric constant oxides." The European Physical Journal-Applied Physics 28.3 (2004): 265-291.
  12. R. K. Baruah and R. P. Paily, “High-temperature effects on device performance of a junctionless transistor,” 2012Int. Conf. Emerg. Electron. ICEE 2012, 2012.
  13. Sahay S, Kumar MJ. Controlling L-BTBT and Volume Depletion in Nanowire JLFETs Using Core–Shell Architecture. IEEE Transactions on Electron Devices. 2016;63(9):3790-3794. doi:10.1109/ted.2016.2591588
  14. Han MH, Chen HB, Yen SS, Shao CS, Chang CY. Temperature-dependent characteristics of junctionless bulk transistor. Applied Physics Letters. 2013;103(13). doi:10.1063/1.4821747
  15. Lü, Wei-Feng, and Liang Dai. "Impact of work-function variation on analog figures-of-merits for high-k/metal-gate junctionless FinFET and gate-all-around nanowire MOSFET." Microelectronics Journal 84 (2019): 54-58.
Support