Search
1311 articles for “Arch”
-
Deep Learning Architectures for Predictive Modeling in Financial Time Series
Abstract: This study investigates the application of deep learning architectures, particularly convolutional neural networks (CNNs), to the challenging task of financial time series forecasting. Financial markets are inherently complex and influenced by a range of factors, making accurate prediction of price movements a difficult problem. In this research, historical financial data including stock prices, volumes, and other relevant indicators are used to train CNN models aimed at capturing the underlying patterns …
Published in Current Trends in Signal Processing · Vol. 15, Issue 3, 2025 · pp. 45–55 Read article
-
A Trust-Enhanced Security Architecture for Authenticating Customer Records in Banking Institutions
Abstract: The growing digital disruption of banking and financial services has completely altered the face of customer onboarding, money transactions, and financial service deliveries. Even as digital technologies provide unparalleled levels of efficiency and accessibility for consumers of financial services, they have also presented new challenges that are equally daunting. Among the growing number of financial threats that digital technology has spawned is the risk of synthetic identity fraud. Unlike identity …
Published in Journal Of Network security · Vol. 14, Issue 1, 2026 · pp. 16–22 Read article
-
Power and Area - Aware Recursive Multiplier Architecture Utilizing Polymer Composites for Neural Network Acceleration
Abstract: Approximate computing is widely applied in error - tolerant systems as an effective technique to enhance circuit performance by deliberately allowing occasional inaccuracies instead of strictly ensuring precise results for every computation. Among the fundamental building blocks of digital systems, multipliers play a crucial role in signal processing, control systems, and machine learning applications; however, they demand significant power, silicon area, and timing resources. Leveraging error - tolerant approximate multipliers …
Published in Journal of Polymer & Composites · Vol. 14, Issue 1, 2026 · pp. 1320–1337 Read article
-
Autonomous 6G Physical Layer Architectures for Space-Air-Ground Integrated Networks
Abstract: The emergence of sixth generation (6G) wireless systems calls for a significant shift away from conventional deterministic communication models. As communication infrastructures evolve into Space- Air-Ground Integrated Networks (SAGIN), traditional physical layer (PHY) techniques struggle to operate effectively under the severe Doppler effects and long propagation delays associated with space environments. This paper examines the role of artificial intelligence embedded directly within the 6G transceiver architecture to enable ultra-reliable and …
Published in Journal of Telecommunication, Switching Systems and Networks · Vol. 13, Issue 2, 2026 · pp. 21–31 Read article
-
A Physics-Informed Graph Neural Network Framework for Real- Time Thermal-Aware Fault Prediction and Adaptive Power Optimization in Heterogeneous System-on-Chip Architectures
Abstract: Heterogeneous System-on-Chip (SoC) architectures are increasingly adopted in edge computing, artificial intelligence, autonomous systems, and high-performance embedded platforms due to their superior computational efficiency and flexibility. However, increasing integration density and workload diversity introduce severe thermal hotspots, accelerated device degradation, and unexpected hardware faults that adversely affect system reliability and energy efficiency. This study proposes a Physics-Informed Graph Neural Network (PI-GNN) framework for real-time thermal- aware fault prediction and adaptive …
Published in Journal of VLSI Design Tools and Technology · Vol. 16, Issue 2, 2026 · pp. 19–28 Read article
-
Implementation of Weighted Round Robin Algorithm in Shared Bus Architectures
Abstract: AbstractThe application domain of System-On-Chips (SoC) includes mobile devices, end terminals, multimedia terminals, automotive, set-top-boxes, games, processors etc. The SoC design paradigm relies heavily on reuse of intellectual property cores, enabling designers to focus on functionality and performance of the overall system. This is possible if IP cores are equipped with highly optimized interface for plug and play insertion into communication architecture. To this purpose the virtual Socket Interface Alliance …
Published in Journal of Electronic Design Technology · Vol. 8, Issue 2, 2017 · pp. 34–40 Read article
-
A Reliable Routing Architecture and Algorithm for Network-on-Chip
Abstract: The Network-on-Chip (NoC) is Network-version of System-on-Chip (SoC) means that on-chip communication through packet based networks. In NOC topology, routing algorithm and switching are main terminology. The routing algorithm is one of the key factors in NoC architecture. The routing algorithm which defines as the path taken by a packet between the source and the destination. The paper proposes a novel algorithm for a Network-on-Chip, which is based on packet …
Published in Journal of Electronic Design Technology · Vol. 6, Issue 3, 2015 · pp. 40–48 Read article
-
Design and Implementation of A 4-bit Multiplier using Wallace Tree Architecture in 180 nm Technology
Abstract: Over the period of last decade, power dissipation has become one of the most important factors for VLSI designers in the design of most digital systems. Even though the speed and area are considered to be the critical factors in design of digital systems, there is a trade of with power consumption. Adders and multipliers are the most important arithmetic units in a processor and the major sources of power …
Published in Journal of Microcontroller Engineering and Applications · Vol. 2, Issue 1, 2015 · pp. 17–23 Read article
-
Behavior of Sandwich Composites under Edgewise and Flatwise Compression; Effect of Variation of Fibre Architecture and Core Density
Abstract: The present paper is focused on the fabrication of foam–cored sandwich composites using manual hand layup technique and testing under in-plane compression. The sandwich construction comprises of polyurethane foams of five varied densities with E-glass fibre in vinylester resin as face sheets. Four different varieties of E-glass fibre are used. As compression properties are of critical importance during the design of lightweight structures, an attempt is made to study the …
Published in Journal of Materials & Metallurgical Engineering · Vol. 5, Issue 1, 2015 · pp. 18–35 Read article
-
Digital Front-End Architecture of ECG Acquisition System with 0.5V Supply
Abstract: AbstractDue to the popularity of portable electronic products, low power systems have attracted more attention in recent years. Dynamic power consumption remains to be the biggest contributor to the total power consumption of a hardware design. A new power efficient electrocardiogram acquisition system that uses a fully digital architecture to reduce the power consumption and chip area has been proposed in this paper. The design of analog-to-digital converters (ADCs) is …
Published in Journal of Semiconductor Devices and Circuits · Vol. 3, Issue 2, 2016 · pp. 11–20 Read article
-
Comparative Analysis of Different SRAM Cells Architecture at 70 nm
Abstract: There are severe constraints which affect the real time operation of SRAM cells. With increasing demand of device scaling, the performance parameters of SRAM cells are affected. Our main purpose is to maintain performance of memory cells in real time operation. Here, we considered three basic parameters stability, leakage current and delay for compression of various SRAM cell architectures. In this paper, we considered conventional 6T, asymmetric 7T, asymmetric 8T …
Published in Journal of VLSI Design Tools and Technology · Vol. 8, Issue 2, 2018 · pp. 33–41 Read article
-
Implementation and Analysis of 32-bit pipelined RISC Processor Architecture
Abstract: Pipelining is an implementation technique, in which parallel operations are performed for several instructions simultaneously, to save time, enhance speed and for better utilization of hardware units. In this paper, 32-bit, 5-stage RISC processor is used to tag the pipeline stages to obtain the optimized results. The architecture of the processor containing several elements reduces the debugs and upholds the high performance through critical functions. When compared to our closest …
Published in Journal of VLSI Design Tools and Technology · Vol. 9, Issue 1, 2019 · pp. 1–14 Read article
-
A Novel Current-Mode Quaternary Multiplier with Indian Vedic Architecture
Abstract: A multiplier is a fundamental block of any digital signal processing system. Urdhva Tiryakbhyam sutra, from ancient Indian Vedic mathematics, offers regular and hierarchical multiplier architecture. Alternatively, current-mode multi-valued logic results in reduced circuitry and effective utilization of interconnections. In this paper, a new 4×4 current-mode quaternary Vedic multiplier design is proposed. The multiplier has been simulated using 0.18 µm technology with a power supply of 1 V and a …
Published in Journal of VLSI Design Tools and Technology · Vol. 4, Issue 2, 2014 · pp. 37–46 Read article
-
GDI Logic Implementation of Variable Sized CSLA Architectures Using 45 nm SOI Technology
Abstract: Carry select adder (CSLA) is an efficient adder used in modern processors. But, the CMOS logic implementation at the transistor level makes it complex. The use of smaller transistor size has shrunk the overall design but the transistor count was retained. Hence, in this paper the transistor level implementation of variable sized CSLA architecture is done using gate diffusion input (GDI) logic. This implementation drastically simplifies the CSLA in terms …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 1, 2016 · pp. 78–88 Read article
-
A Five-Layer Architectural Framework for Sustainable and Scalable AI Systems
Abstract: Artificial Intelligence (AI) is not only about algorithms. AI works like a full “stack” of layers, from electricity to real-world user applications. In this paper, we explain a simple and student-friendly Five- Layer Architecture of AI: (1) Energy, (2) Chips, (3) Infrastructure, (4) Models, and (5) Applications. Each layer supports the next layer, like a cake with multiple layers. If any layer is weak, AI systems become slow, costly, or …
Published in Journal of Artificial Intelligence Research & Advances · Vol. 13, Issue 3, 2025 Read article
-
Text-to-SQL Systems: A Comprehensive Study of Evolution, Architectural Advancements, Challenges, and the Role of Large Language Models in Intelligent Query Generation
Abstract: Interacting with relational databases traditionally requires knowledge of Structured Query Language (SQL), which creates a significant barrier for users who do not have technical expertise. To address this challenge, Text-to-SQL systems have emerged as an important area of research, enabling users to express their information needs in natural language while automatically generating executable SQL queries. These systems aim to make database access more intuitive, efficient, and accessible across a wide …
Published in Journal of Advanced Database Management & Systems · Vol. 13, Issue 2, 2026 · pp. 10–19 Read article
-
A Multi-Layer Architecture for Intrusion Tolerant Web Services
Abstract: Web services as basic building blocks for next generation distributed systems, play a crucial role in these days enterprise application architectures. The flexibleness and openness of the net services computing model will expose company information and business processes to security risks. To support vital applications, the present net service models got to be extended to assure survivability. During this paper we have a tendency to gift a multi-layer design for …
Published in Journal of Advancements in Robotics · Vol. 2, Issue 2, 2015 · pp. 33–39 Read article
-
Internet of Things: A Survey of Architectures and Recent Research Trends
Abstract: Abstract— Internet of Things is a today’s Technology. Research on this technology is in early ages. In IOT Ocean, it is a collection of devices, domains, components, middleware, and protocols. IOT is such a technology, which is improving day by day. IOT is now becoming a part of daily human life. It opens new challenges and research area for researchers. This paper is just an effort to find research possibilities …
Published in Journal of Web Engineering & Technology · Vol. 4, Issue 3, 2017 · pp. 43–61 Read article
-
Domain Specific Parallel Crawler Architecture
Abstract: The World Wide Web is an interlinked gathering of billions of reports organized utilizing HTML. Because of the developing and dynamic nature of the web, it has turned into a test to cross all URLs in the web archives and handle these URLs, so it has ended up basic to parallelize a creeping prepare. The crawler process is further being parallelized in the shape nature of crawler specialists that parallel …
Published in Recent Trends in Parallel Computing · Vol. 3, Issue 1, 2016 · pp. 17–21 Read article
-
A Review on Terminology of Architectures
Abstract: AbstractImportantly, the main concepts of parallel computing were given by John von Neumann and Micheal J. Fylnn. In this paper, the concepts of both of them are given. It is intended to provide only a very quick overview of the coextensive and broad concepts topic of parallel computing, as a lead-in for the paper that follows it. As such, it covers just the very basics of parallel computing, and is …
Published in Recent Trends in Parallel Computing · Vol. 3, Issue 3, 2016 · pp. 5–10 Read article