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43 articles for “Verilog-A”
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Triangular Waveform Generation using Mixed Signal Modeling
Abstract: The development of modeling languages such as Verilog-HDL and Verilog-AMS allows the behavior of analogue and mixed signal circuits to be described with a more lucid way as compared to the conventional circuit-level simulators. Mixed-signal simulators are thus providing a new platform for more efficient modeling of mixed signal that contains both the analogue and discrete features which was not previously possible. The non-linear characteristics of many circuits are still …
Published in Journal of VLSI Design Tools and Technology · Vol. 4, Issue 2, 2014 · pp. 8–17 Read article
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Reusable Verification Framework of AMBA AHB-Lite Protocol using HDVL and UVM
Abstract: Huge complexity of chip increased in the past recent years and integration of more number of transistors on a single SoC makes verification of any SoC based design very critical. About 75–80% of the total design cycle time is spent in functional verification. To reduce this time and effort, hardware verification languages came into picture. The most popularly used HVL is system verilog, which is based on object oriented programming …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 2, 2016 · pp. 62–73 Read article
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Coverage Driven Verification of Synchronous FIFO using UVM
Abstract: FIFO (first in first out) is a memory array in which the data written first into the memory will be read first with the help of the control signals read and write where the control signal write is used to write the data into the memory and the control signal read is used to read the data from the memory. To avoid the memory overflow and to know that whether …
Published in Recent Trends in Electronics Communication Systems Read article
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Different Compressor Adders
Abstract: AbstractMultipliers are one of the main blocks which decide the circuit performance as well as computation speed. In multiplication, addition of partial products contributes most to the circuit delay, power, and area. In this project, compressor adders are used to reduce this delay. Hence, compressors are a major part of the multiplier circuit that decides the overall speed of the system. For high-speed processing and higher systems, a huge number …
Published in Journal of Semiconductor Devices and Circuits · Vol. 5, Issue 2, 2018 · pp. 19–26 Read article
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Practical Implementation of Network Switch on FPGA
Abstract: AbstractA network switch is a hardware device, which is used for device communication within a network. It uses a packet-switching mechanism to receive and transmit data to the target device. Network switches contain multiple ports that use media access control (MAC) address for transmitting data at the data link layer (layer 2) of the Open Systems Interconnection (OSI) model. This research aims to design a network switch on FPGA to …
Published in Journal of Telecommunication, Switching Systems and Networks · Vol. 7, Issue 1, 2020 · pp. 14–19 Read article
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Design of Three-Stage Pipelined Floating Point Arithmetic Operators
Abstract: Some embedded systems perform signal processing operations (Fourier transform, filtering) as for example for the recognition voice, high quality audio and control of critical systems (airplane, rocket). This type of operation may require the use of floating numbers. This paper presents the hardware implementation of floating point arithmetic operators for addition, subtraction, multiplication using the IEEE-754 single precision format. Proposed architecture follows two different RTL approach, Melay FSM and multiplexer …
Published in Journal of VLSI Design Tools and Technology · Vol. 8, Issue 2, 2018 · pp. 9–22 Read article
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Hardware Optimization of FPGA for I2C Master Protocol and Interfacing with EEPROM Slave
Abstract: This paper focuses on I2C (Inter Integrated Circuit) protocol master controller. I2C protocol was originally given by Philips semiconductors so that faster devices can communicate with slower devices and also allow devices to communicate with each other over serial bus without data loss. The I2C controller provides support for a communication link between integrated circuits and memory units on a board. I2C is a bidirectional serial bus which contains two …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 2, 2015 · pp. 42–48 Read article
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Design and RTL Implementation for AHB-APB Bridge on SoC
Abstract: The focus of this research is to design and implement an interconnection protocol with 32-bit read/write data which operates on AMBA AHB-APB bridge. With the advent of scaling technology, embedded system focuses more on low-power dissipation and SoCs. Hence processors and routing protocols which focus on low-power design by ARM have gained popularity. In high-speed communication modules, the protocol works efficiently but has limitations with device operating at low speed. …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 2, 2016 · pp. 44–52 Read article
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Implementation of Adders Using Ternary Based Multiple Valued Logic
Abstract: In today’s world VLSI chips are widely used in various branches of Engineering like Voice and Data communication networks, Digital signal processing, Computers, Commercial Electronics, Automobiles, Medicine and many more. So, there have been major advances in IC technology which have both made feasible and generated great interest in electronic circuits which employ more than two discrete levels of signals such circuits called Multiple valued logic circuits, offer several potential …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 1, Issue 2, 2023 · pp. 1–8 Read article
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Design and Implementation of Low Latency 16-bit Full Adder
Abstract: In the new age world, modern technology has vast applications in various fields of engineering, medicine, and others. Digital electronics processing and systems play a vital role in the analysis and computation of data representation. Electronic systems have gradually become faster and smaller scale. The primary structural element of any modern ALU-based processor is an adder. Addition is a well-known extremely basic function that is employed in nearly all computing …
Published in Journal of VLSI Design Tools and Technology · Vol. 14, Issue 3, 2024 · pp. 21–31 Read article
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32-bit Single Cycle MIPS RISC Processor
Abstract: In this report, I have written a Verilog HDL code for the MIPS 32-bit single-cycle RISC Processor and simulate the same. I have derived the result in four points first in terms of resource utilization, an RTL design view, TTL design view, and perform simulation on emulator using machine code. The topics I have cover the report are how to define instruction set for RISC architecture? Designing of various digital …
Published in Current Trends in Signal Processing · Vol. 12, Issue 1, 2022 · pp. 29–37 Read article
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Design and Verification of Low Power High Speed Voltage Level Shifter Based on Pass Transistor Methodology
Abstract: This study explains how a voltage level shifter (LS) can be built using a Wilson current mirror level shifter (WCMLS) with a mirrored output. The proposed fix avoids WCMLS's typical issue of requiring a mirror with a size ratio that is too large. It's a space- and cost-saver. The proposed LS requires less components than its modern versions and uses only tiny components, taking up even less space. The proposed …
Published in Journal of Control & Instrumentation · Vol. 14, Issue 2, 2023 · pp. 30–37 Read article
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Detection of Fault and Protection of Faulted Distribution Feeder with Field Programmable Gate Array Using State Diagrams
Abstract: A hardware-efficient algorithm for fast fault-detection in feeders radiating out of a distribution substation and its subsequent clearance from the system for safe operation of the healthy parts has been presented in the paper. State diagrams used to design the circuit.The general purpose SPARTANE 3AN FPGA kit has been employed for developing the protective over-current relay. All the coding has been done using the hardware description language VERILOG. To avoid …
Published in Journal of Microcontroller Engineering and Applications · Vol. 2, Issue 2, 2015 · pp. 5–12 Read article
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A Novel Architecture of Control System Processor Using Field Programmable Gate Array
Abstract: This paper presents a reconfigurable architecture of control system processor. The performance of the proposed architecture has been evaluated by taking different controllers and phase lead and phase lag networks. We designed the architecture of the processor and realizing the architecture using adder, multiplier, delay unit and validate it in the FPGA, which show that the hardware scheme is feasible for practical application. The experimental results clearly reveal the novelty …
Published in Journal of Microcontroller Engineering and Applications · Vol. 2, Issue 2, 2015 · pp. 13–20 Read article
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Implementation of FIR Filter with Reverse Converter based RNS Kogge–Stone Adder
Abstract: AbstractLow power very large scale integration (VLSI) circuits are pertinent for designing of steep overall performance and adjustable devices. In current technology VLSI plays a vital role to reduce power consumption and delay. In analog to digital converter process, adder plays a crucial role. The authority of nonviolent issue is increasing regularly because of changing that a way, packaging and cooling cost, transportable route of motion and reliability. This freebie …
Published in Journal of Microelectronics and Solid State Devices · Vol. 5, Issue 2, 2018 · pp. 34–43 Read article
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A Novel Register Minimization Technique for Efficient Implementation of BLMS Filter
Abstract: Purpose: This paper presents a novel register minimization technique for the BLMS filter. The purpose is to reduce the number of registers leading to reduction in hardware resource used for BLMS filter and thus reducing the complexity. Design/Methodology/Approach: In the BLMS filter due to substantial number of register and hardware resource, Strassen’s algorithms are used to minimize the registers. Strassen’s algorithm is used for the matrix multiplication in the BLMS …
Published in Journal of Microelectronics and Solid State Devices · Vol. 4, Issue 2, 2017 · pp. 18–31 Read article
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Implementation of UART with CALBO
Abstract: The increasing growth of submicron technology has resulted in the difficulty of VLSI testing for designers who always look for simple and cost effective logic structure to realize a complex function. Thus Automatic Testing Equipment (ATE) is becoming costly process for testing. To reduce the cost of testing the chips, Built in Self-Test (BIST) has emerged as a cheaper alternative. BIST is a design technique that allows the chip to …
Published in Journal of Microelectronics and Solid State Devices · Vol. 2, Issue 1, 2015 · pp. 6–12 Read article
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An Efficient RNS Based Sparse Kogge Stone Parallel Pre-fix Adder with Filter
Abstract: AbstractLow power very large-scale integration (VLSI) circuits are important for designing of high performance and portable devices. Along with that the high speed, small area and low cost are also the main considerations of VLSI circuits. The importance of low power is increasing day by day because of changing trend, packaging and cooling cost, portable system and reliability. This paper presents the design of Digital FIR filter using reverse converter …
Published in Journal of Semiconductor Devices and Circuits · Vol. 5, Issue 1, 2018 · pp. 43–51 Read article
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Design of 16-bit Pipelined RISC Processor
Abstract: This paper presents the design of efficient and high throughput 16-bit pipelined RISC Processor. The design is challenge with the pipelined stall problem, speed with external memory, coding density and clock frequency for cost effectiveness and higher performance processor design. Paper describes about the architecture, programming model, synthesis results and analysis of the design. The presented design has throughput ~167 MIPS at 500 MHz, which shows better performance at a …
Published in Journal of VLSI Design Tools and Technology · Vol. 2, Issue 1-2-3, 2012 · pp. 32–37 Read article
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Design of Booth Encoded Multi-Modulus {2n-1, 2n, 2n+1} RNS Multiplier
Abstract: Multiplication, a very important arithmetic operation, is finding a great use these days in various applications (especially DSP, multimedia and image processing). Due to advances in technology and increasing needs for high-speed calculations, it has become really necessary and important to design a fast efficient multiplier. A productive method to speed up the multiplication is reduction in the Partial Product (PP) array. In this paper, the design of 8, 16 …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 3, 2016 · pp. 7–14 Read article