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108 articles for “Static Power”
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A Novel Design for Power Reduction in Arithmetic Circuits using MTCMOS Technology
Abstract: In CMOS logic circuits, the reduction in the threshold voltage due to voltage scaling leads to increase in the subthreshold leakage current and hence static power dissipation. Although power consumption is important for modern VLSI design, operation speed and occupied area are still the main requirements of the VLSI design. Multi threshold voltage CMOS (MTCMOS) technology is a good solution which provides a high performance and low-power design without any …
Published in Journal of VLSI Design Tools and Technology · Vol. 4, Issue 1, 2014 · pp. 1–7 Read article
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Dynamic Comparators for Very High-Speed ADC’s
Abstract: The need for ultra- low power and space economical analog –to- digital converters (ADCs) is pushing towards the utilization of low voltage CMOS dynamic comparators to maximise the facility potency and speed. the traditional dynamic comparators have options like high input ohmic resistance, no static power dissipation and sensible strength against noise and couple. the downside is that giant numbers of transistors are accustomed minimize the offset, therefore the speed …
Published in Recent Trends in Fluid Mechanics · Vol. 8, Issue 3, 2021 · pp. 32–45 Read article
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Implementation and Simulation of High-Speed Dynamic Latch Comparator for ADC
Abstract: As per emerging issues in analog-mixed signal (AMS) design towards high-speed and low power, limits the performance of high-speed applications. Circuit complexity, speed, offset voltage and resolutions are essential parameter of comparator that affects the analog-to-digital converter (ADC) performance. Based on specifications, to achieve lower offset voltage and higher load drivability of latched comparator is presented. Moreover, the circuit is able to reduce power dissipation as the topology is based …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 2, 2016 · pp. 99–103 Read article
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Design and Implementation of Low-power SPI Shift Register
Abstract: SPI stands for serial peripheral interface which is used for serial, synchronous and full duplex communication of data between master and slave devices. Master devices can be Microprocessors or Microcontrollers; and slaves are the Peripheral devices interfaced with them. The main internal component for architecture of master/slave block is shift register which defines its operation. But as the size of the shift register increases, power is utilized to a greater …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 1, Issue 1, 2023 · pp. 1–15 Read article
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A 32-Bit Booth Multiplier Design Using GDI Logic Style
Abstract: Gate diffusion input (GDI) is the newest technology of designing a low-power digital combinational circuit. This logic allows reducing power dissipation, delay and area of any digital logic circuit. The gate diffusion input logic allows implementation of a wide range of any complex logic function. These functions can be realized using only two transistors. This technique is preferred for designing fast using less number of transistors while improving logic level …
Published in Trends in Electrical Engineering · Vol. 5, Issue 3, 2015 · pp. 1–5 Read article
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Design and Implementation of Low Noise Power Low and High Speed Three Stage Comparator Using 16nm Technology
Abstract: To meet the demands of quicker operation and reduced noise levels, this study proposes a new CMOS Three-based comparator version. Efficiency may be significantly improved by comparing the suggested model to existing ones. This is so because the suggested comparator would improve the efficiency of the current amplifier design. The suggested model drives the input pairs of the regenerator and the amplified stage, making for a quicker comparator. The structure …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 1, Issue 2, 2023 · pp. 10–16 Read article
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Power Quality Enhancement in Distribution System using D-STATCOM
Abstract: New solutions based on power electronics have been developed to safeguard commercial and industrial clients against power quality issues on the electrical distribution system, referred to as Custom Power Products. Custom power devices are classified into three categories by their structures such as dynamic voltage regulator (DVR), distribution static compensator (STATCOM) and unified power quality compensator (UPQC).The Distribution Static Compensator (D-STATCOM), one of the custom power product, is a shunt-connected …
Published in Recent Trends in Electronics Communication Systems · Vol. 8, Issue 2, 2021 · pp. 17–22 Read article
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A Review on STATCOM Controller for Power Quality Enhancement in Distributed System
Abstract: New technologies, using power Electronics-based concepts, have been Developed to provide protection for Commercial and industrial customers from Power quality problems on the electrical Distribution system known as Custom Power Products. Custom power devices are classified into three categories by their structures such as dynamic voltage regulator (DVR), distribution static compensator (STATCOM) and unified power quality compensator (UPQC).The Distribution Static Compensator (D-STATCOM), one of the custom power product, is a …
Published in Trends in Electrical Engineering · Vol. 11, Issue 2, 2021 · pp. 24–29 Read article
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Development of Polymer Based SRAM Cell with Enhance Low Power Performance
Abstract: Low-power memory technologies are in high demand with the rapid growth of portable electronics and energy-efficient computing systems. Static random-access memory (SRAM) plays a crucial role in processors, cache memories, and system-on-chip applications due to their speed and reliability. Static Random Access Memory (SRAM) is typically implemented using complementary MOS (CMOS) technology, which integrates both PMOS (P-channel Metal–Oxide–Semiconductor) and NMOS (N-channel Metal–Oxide–Semiconductor) transistors. However, as technology scales to deep submicron …
Published in Journal of Polymer & Composites · Vol. 14, Issue 1, 2026 · pp. 1439–1448 Read article
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Advanced Mathematical Modelling of Nanoscale Semiconductor Devices for Low-Power Microelectronic Applications
Abstract: With the ongoing scaling down of semiconductor devices, there is an increasing need for accurate mathematical models of electrostatic control, carrier transport, leakage current, and power consumption at the nanometer scale. As the sizes of semiconductors continue to decrease, there is a growing need for accurate mathematical models of electrostatic control, carrier transport, leakage current, and power consumption at the nanometer scale. In this work, a common mathematical modelling approach …
Published in Journal of Microelectronics and Solid State Devices · Vol. 13, Issue 2, 2026 Read article
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Enhancing Voltage Stability Assessment through Phasor Measurement-Based Voltage Estimation
Abstract: Voltage stability monitoring of real-time systems may benefit greatly from recent advances in Phasor Measurement Units (PMUs) technology. Based on measurements taken from PMUs at three different operating locations, this article suggests quadratic fitting of nose curves (loading factor against bus voltage magnitude curves). Comparisons between the proposed estimation of nose curves and an existing method of quadratic nose curve fitting based on two step continuation power flow have been …
Published in Trends in Electrical Engineering · Vol. 13, Issue 3, 2023 · pp. 7–15 Read article
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A Circuit Approach for CMOS VLSI Circuit Leakage Power Reduction
Abstract: Despite the fact that scaling CMOS technology boosted speed, leakage currents always remained an issue. The issue has gotten worse as the scaling has gone into the UDSM (ultra-deep-submicron) range. In order for the circuit to function effectively, these unwanted leakage currents must be reduced to a minimum. It is challenging to create these leakage-free nano-scale CMOS circuits. In this work, the issue of leakage power is addressed, which occurs …
Published in Research & Reviews: A Journal of Embedded System & Applications · Vol. 10, Issue 3, 2022 · pp. 7–18 Read article
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A Novel PWM Based STATCOM Controller for Power Quality Enhancement in Distributed System
Abstract: Static Synchronous Compensator has the capability for the improvement in damping factor and stability by managing the reactive power output. As the STATCOM will itself absorb the reactive power which comes from the distribution line when we apply the capacitive load. To get the higher performance of STATCOM we are mainly depend over control algorithms. As the real power factor has been absorb by the STATCOM at the time when …
Published in Journal of Microelectronics and Solid State Devices · Vol. 8, Issue 2, 2021 · pp. 24–32 Read article
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Performance Analysis of Fe/SiO2/Fe MTJ and Ni/Al2O3/Ni MTJ-based Magnetoresistive Random Access Memories (MRAMs)
Abstract: This paper reports the first principle simulations of Fe/SiO2/Fe and Ni/Al2O3/Ni magnetic tunnel junctions (MTJs). A performance analysis has been done based upon the device-level simulations of the two magnetic tunnel junctions followed by the circuit level simulations of magnetoresistive random access memory (MRAM) cell operating with the two MTJs respectively. From the device-level simulations, the two MTJs have been compared with regard to the bias dependence of TMR ratios, …
Published in Journal of VLSI Design Tools and Technology · Vol. 2, Issue 1-2-3, 2012 · pp. 92–100 Read article
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Improvement in Distribution System Performance by D-STATCOM
Abstract: Increasing use of power electronics devices in modern power system has many power quality problems arise in distribution system like voltage sag, voltage swell, harmonics, flickering, etc. This problem largely affects the performance of distribution system. Distribution static synchronous compensator (D-STATCOM) is a device which is used for the solution of power quality problems. In this paper, voltage sag and voltage swell were generated and mitigation of the same is …
Published in Journal of Power Electronics and Power Systems · Vol. 6, Issue 2, 2016 · pp. 25–33 Read article
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Sinusoidal Pulse Width Modulation Switching Technique based Single Phase Inverter
Abstract: This paper discusses about the inverter which transfers power from DC source to AC load side. Inverters are usually used in motor drive, static var compensators, uninterruptible power supplies (ups), etc. Pulse Width Modulation (PWM) technique is used because the total harmonics distortion is low as compared with other techniques. The switching scheme of sinusoidal PWM permits control of the frequency and the magnitude of the output. This switching scheme …
Published in Journal of Power Electronics and Power Systems · Vol. 9, Issue 1, 2019 · pp. 34–41 Read article
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Design of 10T SRAM Cell for Low Power and High Speed Applications
Abstract: AbstractThis paper presents techniques for designing a low-power and higher read speed Static Random Access Memory (SRAM) cell. The cell achieves low power dissipation due to Virtual Ground (VGND) scheme and provides higher read performance due to Forward Body Biasing (FBB). Design metrics of the proposed SRAM cell was studied and compared with that of CON 6T, CON D10T, TG 8T, 9T, and ST-10T SRAM cells. It was observed that …
Published in Journal of Electronic Design Technology · Vol. 8, Issue 2, 2017 · pp. 16–27 Read article
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RTL to GDSII Implementation UART using Verilog and Cadence tools
Abstract: The paper outlines a thorough design flow for Universal Asynchronous Receiver and Transmitter (UART) utilizing Register Transfer Level (RTL) to Graphic Data System II (GDS II) Implementation using Verilog and Cadence tools. The process involves RTL design, logic synthesis with Genus and physical design using Innovus, followed by verification steps including formal verification, static timing analysis and power optimization. The results demonstrate an efficient workflow, highlighting the effectiveness of Cadence’s …
Published in Journal of VLSI Design Tools and Technology · Vol. 15, Issue 1, 2025 · pp. 1–7 Read article
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Power Analysis Comparison of Gated Diode Dram Cell Design on 32 nm Technology
Abstract: In this paper power consumption of Gated diode DRAM (Dynamic Random Access Memory) cells are carried out. This analysis is carried out on 32 nm scale. The DRAM cell used here are 3T1D and 2T1D DRAM cell. Static, total average and transient power for both types of cells are simulated in order to have a comparison of their performance on the same technology. A comparative study of different types of …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 1, 2015 · pp. 19–23 Read article
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Designing and Testing of various types of SRAM topologies with 90nm Technology
Abstract: VLSI technology provides a way for designing compact devices which are useful to human for leading their day to day, the advancement in the technology provides high speed and power consuming appliances. In this category, intend to design an application with high data rate and low power, memory efficient device and Static Random-Access Memory (SRAM) is structured. Improvement in the technology comprises of scaling down the design process and impact …
Published in Journal of Electronic Design Technology · Vol. 13, Issue 1, 2022 · pp. 12–16 Read article