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33 articles for “Drain voltage”
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Machine Learning Assisted Optimization of Nanoscale MOSFET Parameters Using TCAD Simulation
Abstract: This paper presents a machine learning (ML) assisted framework for the multi-objective optimization of nanoscale bulk n-channel metal-oxide-semiconductor field-effect transistors (nMOSFETs) with a 10 nm physical gate length, high-k HfO₂ gate dielectric, and TiN metal gate. Technology computer-aided design (TCAD) simulations employing drift-diffusion transport, Shockley-Read-Hall recombination, Lombardi mobility degradation, and density- gradient quantum correction models are used to generate a parametric dataset of 2,400 device configurations spanning gate length (L), …
Published in Journal of Microelectronics and Solid State Devices · Vol. 13, Issue 1, 2026 · pp. 10–19 Read article
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Design and Optimization of Nano scale Double Gate SOI-MOSFET for Analog Applications Using SILVACO TCAD
Abstract: In this paper the structure effect on electrical characteristics of 60-nm double-gate Silicon-on-Insulator Metal-Oxide-Semiconductor Field Effect Transistor (DG-SOI-MOSFETs) is explored. These structures enable more aggressive device scaling in nano scale region because of their ability to control short channel effects. Established a scaling theory which gives guidance for the device optimization (Silicon film thickness Tsi (20nm); gate oxide thickness Tox (3nm); buried oxide thickness Tbox (200nm) and gate length LG …
Published in Journal of Electronic Design Technology · Vol. 1, Issue 1-3, 2011 · pp. 7–17 Read article
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Analysis of DIBL Effect in MOSFET Working
Abstract: AbstractOne of the most widely used electronic devices, particularly in digital integrated circuits, is the metal insulator semiconductor (MIS) transistor. Most of the existing transistors used in fabrication of integrated chips are with junctions. The device scaling is growing the channel length between junctions in devices are scaling gone down to 10 nm. Drain Induced Barrier Lowering (DIBL) effect is prominent as the feature size of MOS device keep diminishing. …
Published in Journal of Microelectronics and Solid State Devices · Vol. 5, Issue 3, 2018 · pp. 33–40 Read article
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Optimization and Analysis of InGaAs Vertical Nanowire Transistor for Memory Array Applications
Abstract: In this paper, we present a cylindrical gate all around In 0.53 Ga 0.47 As Vertical Nanowire Transistor (VNWT) on silicon at ultra-shortchannel gate length 14nm by numerical simulation approach. The In 0.53 Ga 0.47 As VNWT device dimensions like diameter, source and drainextension length and channel doping are taken as critical process parameters and optimized for better performance. The proposed device isscalable up-to 10nm with a maximum On-current of …
Published in Journal of VLSI Design Tools and Technology · Vol. 13, Issue 2, 2023 · pp. 32–44 Read article
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A Dual Material Control Gate Tunnel Field Effect Transistor for an Asymmetric Doping at Source and Drain Regions
Abstract: Double-Gate tunnel FET devices, which uses high-κ gate dielectric, are explored using realistic design parameters, showing an ON-current as high as 0.23 mA, a gate voltage of 1.8 V, an OFF-current of not more than 1 fA (neglecting gate leakage), an improved ordinary subthreshold swing of 57 mV/dec, and a lower point slope of 11 mV/dec. A dual material control gate tunnel field effect transistor for an asymmetric doping at …
Published in Journal of VLSI Design Tools and Technology · Vol. 8, Issue 3, 2018 · pp. 45–53 Read article
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SPICE Modeling of LDMOSFET Transistor
Abstract: AbstractHigh voltage integrated circuits, these days are the most viable alternatives to discrete circuits for various applications. The popular amongst them is the lateral double diffused MOS transistor (LDMOS). It is based on the lightly doped drain (LDD) concept. The constraint that occurred in modeling LDMOS is to minimize the on-resistance along with maintaining a high breakdown voltage. To achieve the objective, the help of RESURF (Reduced Surface Field) concept …
Published in Journal of Semiconductor Devices and Circuits · Vol. 3, Issue 1, 2016 · pp. 42–57 Read article
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Advanced Mathematical Modelling of Nanoscale Semiconductor Devices for Low-Power Microelectronic Applications
Abstract: With the ongoing scaling down of semiconductor devices, there is an increasing need for accurate mathematical models of electrostatic control, carrier transport, leakage current, and power consumption at the nanometer scale. As the sizes of semiconductors continue to decrease, there is a growing need for accurate mathematical models of electrostatic control, carrier transport, leakage current, and power consumption at the nanometer scale. In this work, a common mathematical modelling approach …
Published in Journal of Microelectronics and Solid State Devices · Vol. 13, Issue 2, 2026 Read article
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Influence of Dielectric and Active layer Thickness on MgZnO Thin Film Transistor Electrical Characteristics
Abstract: From last decades, Thin Film Transistors Technology uses low-k dielectric material as an insulator. Insulator thickness plays an important role in device dimension. The insulating layer also known as the gate oxide separates the gate electrode from the channel region of the transistor. If the insulating layer is too thin, there is a greater chance that electrons can tunnel through the oxide layer, leading to leakage current. To mitigate this …
Published in Journal of Polymer & Composites · Vol. 11, Issue 5, 2023 · pp. 17–26 Read article
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A Comparative Study on Carbon Nanotube MOSFET, Silicon Nanowire MOSFET and Single Gate MOSFET
Abstract: Among many of the concerns for the researchers in nano-electronics, Single Gate MOSFET, Silicon Nanowire MOSFET and Carbon Nanotube MOSFET were very popular three. All of them are different in their structures and performance. This paper is focused on the comparison of their characteristics in terms of Current- voltage relations, Mobility charge density and Quantum capacitance. ‘FETToy’ in ‘nanohub’ was used to simulate the predefined models in room temperature. Drain …
Published in Journal of Electronic Design Technology · Vol. 6, Issue 2, 2015 · pp. 7–12 Read article
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Influence of Graded Channel on Performance of Symmetric Double Material Gate Insulator FDSOI MOSFET
Abstract: Abstract: In this paper, we investigate the effect on the linearity, analog and RF performance of graded channel in case of hetero-gate-dielectric FDSOI MOSFET with higher doping at source end and low doping at drain end. The major figure of merits (FOMs) studied are on-state drive current (ION), transconductance (gm), total gate capacitance (Cgg), cut-off frequency (fT), higher order derivative of transconductance (gm’, gm’’), intermodulation distortion (IMD3) and third- order …
Published in Journal of Microelectronics and Solid State Devices · Vol. 6, Issue 1, 2019 · pp. 12–17 Read article
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A Review on High Electron Mobility Transistors
Abstract: AbstractThe demand for high speed semiconductor devices is increasing in recent years with the rapid development of the high frequency wireless and fiber optical communication systems. High electron mobility transistor (HEMT) is an important device and an excellent candidate for millimeter, sub-millimeter and microwave applications. Also, these devices have high frequency, high speed, low noise, high breakdown voltage, low cost and other power handling capabilities. Due to these reasons, they …
Published in Journal of Semiconductor Devices and Circuits · Vol. 3, Issue 2, 2016 · pp. 1–10 Read article
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Seasonal Variation of Electric Vehicles Autonomy: Application to AC/DC Dual Voltage Operation
Abstract: In this work, a study to predict battery performance and autonomy for a dual type of electric engine, 480 VAC and 360 VDC, has been developed. The study has been conducted in vehicles of mass between 1000 and 3000 kg with battery capacity in the range of 40 to 100 kWh. The process has been simulated using reference values and modeled for specific driving conditions. The simulation has been developed …
Published in Journal of Mechatronics and Automation · Vol. 7, Issue 3, 2020 · pp. 1–15 Read article
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Investigation and Dependency Analysis of Silicon Film Thickness on Performance of Surrounding Gate MOSFET at Subthreshold Regime
Abstract: The characteristics of cylindrical gate all around MOSFET have been studied in terms of the dependence of various device performance metrics on silicon film thickness (Tsi). In this work, the effect of silicon film thickness on numerous performance metrics like threshold voltage (Vt), On current (Ion), subthreshold leakage current (Ioff), On-Off current ratio (Ion/Ioff) and DIBL of cylindrical GAA are comprehensively evaluated and analysed. It has been observed that cylindrical …
Published in Journal of VLSI Design Tools and Technology · Vol. 8, Issue 2, 2018 · pp. 49–54 Read article