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136 articles for “CMOS Circuit”
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Performance Analysis of Bootstrapping Techniques to Overcome the Threshold Voltage Drop in NMOS Logic Design
Abstract: Abstract: In this paper, we study the concept of bootstrapping techniques and analyzed its performance in digital CMOS circuits. These bootstrapping circuits are used to increase the gate voltage of transistors so that drain node voltage can be pulled high to overcome the threshold voltage drop problem in NMOS logic design. Also discuss the drawback associated with voltage bootstrapping techniques in NMOS logic design that is sneak path problem between …
Published in Journal of Semiconductor Devices and Circuits · Vol. 6, Issue 1, 2019 · pp. 15–20 Read article
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1-Bit Full Adder's Analysis and Comparison
Abstract: The full adder circuit forms the basis of majority of digital circuits. Improvement in a basic full adder circuit in terms of area, power and delay affect the performance of whole system. It becomes compulsory to investigate and analyze the performance of implementation of full adder circuit in literature, till now. In this paper, a study is carried out to look into performance parameters of full adder circuit using different …
Published in Journal of Electronic Design Technology · Vol. 6, Issue 2, 2015 · pp. 1–6 Read article
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Unified Mathematical Framework for Semiconductor Devices, Junction Dynamics, and Circuit Analysis
Abstract: Semiconductor devices form the fundamental building blocks of modern electronic and integrated circuit systems, where their electrical behavior is governed by coupled carrier transport, electrostatic, and circuit-level phenomena. This work presents a unified mathematical framework for modeling semiconductor devices, junction dynamics, and their interaction with electronic circuits. The formulation integrates fundamental semiconductor relations, carrier concentration, drift–diffusion transport, Poisson’s equation, continuity equations, PN-junction behavior, diode characteristics, bipolar junction transistor operation, and …
Published in Journal of Semiconductor Devices and Circuits · Vol. 13, Issue 2, 2026 · pp. 37–47 Read article
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Characterization of High Performance Third Generation Current Conveyor using CMOS Technology
Abstract: In this paper, Conventional Third generation(CCIII) and Dual-Output Cascoded Third Generation Current Conveyor(DOCCIII) is presented. Here, both are simulated in ELDO SPICE Mentor Graphics using 90 nm CMOS technology at 0.8 V supply voltage. High performance cascoded current mirrors provide high output impedance. Third generation current conveyer has the advantages of wide current and voltage bandwidths, controlled intrinsic resistances at terminals X,Y and Z. By the use of high performance …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 2, 2015 · pp. 54–63 Read article
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Comparative Study of (Operational Transconductance Amplifier) OTA to Design Low Pass Filter
Abstract: Basic building block to design an analog circuit is amplifier and it is used for such applications like analog to digital and digital to analog converter, sensor network and many more. Amplifier with lofty gain and high bandwidth will increase the efficiency of design. Present time is talking about development of VLSI technology and everything is related to size of transistor and decreasing power supply in a circuit. Operational transconductance …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 2, 2015 · pp. 11–15 Read article
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Understanding of optical power in semiconductor based SOI Structure at the signal 1550 nm
Abstract: A silicon-on-insulator (SOI) structure consists of a single crystalline silicon layer separated from the bulk substrate by a thin insulator layer. The insulator in SOI wafers is usually always a thermal silicon oxide (SiO2) layer, with a silicon wafer as the substrate. The silicon sheet can be very thin (50 nm for fully depleted transistors) or tens of micrometres thick, depending on the application. Similarly, the thickness of buried oxide …
Published in Trends in Opto-electro & Optical Communication · Vol. 12, Issue 1, 2022 · pp. 19–23 Read article
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Design of Low Noise Transimpedance Amplifier using Multiple Feedback filter Topology
Abstract: This study presents the highly linear and low noise transimpedance amplifier (TIA) based on CMOS inverter as an amplifier within multiple feedback (MPFB) filter topology. Absence of complex analog circuitry and compatibility with widespread digital CMOS processes highlight this TIA topology asthe best choice in signal conditioning chains approaching analog-to-digital converters (ADCs). Special attention has been given to the TIA stability and compensation networks. Using dedicated low-dropout (LDO) regulator, the …
Published in Journal of Electronic Design Technology · Vol. 13, Issue 1, 2022 · pp. 25–30 Read article
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Low power high performance CMOS Schmitt Trigger using nanoscale CMOS Technology
Abstract: This paper presents different low voltage adjustable CMOS Schmitt trigger at 90nm technology. This paper proposes the transient response and noise response analysis of CMOS Schmitt trigger circuit which will give noisy input signals with less noise response and also applicable for low power. It enumerates reduction of power consumption, which is in major demand in the field of VLSI. The CMOS device is used to achieve better power consumption, …
Published in Journal of Mobile Computing, Communications & Mobile Networks · Vol. 5, Issue 1, 2018 · pp. 28–35 Read article
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Comparative Analysis of Low-Power Adiabatic Techniques
Abstract: In today’s modern era, new revolutionary designs are replacing old traditional bulky designs. Due to advancements in technology, low-power designs are in demand. Advantages of adiabatic technique can be used for overcoming disadvantages of typical CMOS such as dissipated energy loss. Adiabatic techniques are extremely reliant on parameter changes. In this paper, the merits of adiabatic techniques are depicted on the basis of parameter variations. By the use of SPICE …
Published in Journal of VLSI Design Tools and Technology · Vol. 4, Issue 2, 2014 · pp. 53–58 Read article
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Performance Analysis of CMOS and FinFET Based SRAM
Abstract: As CMOS devices are scaled to nanometer regime, the consequences such as short channel effects and variations in the process parameters are increased which affects the reliability and performance of the circuit. In order to over these issues, FinFET can be used as a suitable replacement for CMOS as it is a promising and better technology without sacrificing the reliability and performance of the applications and the circuit design. In …
Published in Journal of VLSI Design Tools and Technology · Vol. 8, Issue 3, 2018 · pp. 23–27 Read article
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Design of Low-speed CMOS AM-Transceiver
Abstract: The design of Low-speed AM-transceiver for sensors circuit in CMOS technology is described. A non-standard topology and accurate sizing of the transistors allow full integration and operation down to supply voltage of 5V. We detail the design to the transistor level with special consideration to the limitations associated with low supply voltage. We emphasize the careful sizing of transistors. Keywords: CMOS, AM-Transceiver, Transistor
Published in Journal of Microcontroller Engineering and Applications · Vol. 1, Issue 2, 2015 · pp. 34–43 Read article
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A New Sub-1 Volt Reference for Low Voltage Application Based on MOSFET’s Threshold Voltage Extractor
Abstract: A CMOS voltage reference circuit featuring MOS transistors threshold voltage extractor has been developed. The circuit implemented using 0.35µm CMOS AMS process generates a reference of 574 mV for a power supply of 3.3V with 726µW power consumption. The circuit presents a variation of 43 ppm/ºC for the –10 to –110ºC temperature, and 18.6 dB PSRR at 1 KHz. A vital analytical approach is presented to provide a universal design …
Published in Journal of VLSI Design Tools and Technology · Vol. 3, Issue 1, 2013 · pp. 14–19 Read article
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Detailed Study of Working and Applications of FinFET Technology and Its Adaptability in Current Era
Abstract: The CMOS technology is following Moore’s law since almost 25 years. The scaling of CMOS transistor has increased packaging density, speed and decreased power dissipation in the integrated circuits. However, CMOS dimension when scaled to nanometer dimension, many physical barriers arise. In sub-100 nm scale, MOSFET has new variants as SOI implementation and double gate. Keywords: Silicon on insulator (SOI), short channel effect (SCE) [2], buried oxide (BOX)
Published in Journal of VLSI Design Tools and Technology · Vol. 2, Issue 1-2-3, 2012 · pp. 52–58 Read article
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High Speed and Low Power Basic Digital Logic Gates, Half-Adder and Full-Adder Using Modified Gate Diffusion Input Technology
Abstract: In this paper, modified gate diffusion input (MGDI) technology has been used for the design and implementation of digital integrated circuits (ICs). In today’s digital world, IC plays a vital role in high-performance computing, communication, and many consumer electronics. IC manufacturing technology has scaled down to smaller device dimensions. This scaling has a great impact on the design of digital ICs. The main objective of the IC manufacturing technology is …
Published in Journal of VLSI Design Tools and Technology · Vol. 8, Issue 1, 2018 · pp. 34–42 Read article
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Power Reduction at 90 nm through Circuit Level Modification
Abstract: Along with dynamic power, leakage power has turned out to be a major contributor to the overall power consumption in VLSI circuits. This problem is even more stringent in nano-scale dimension devices according to the International Technology Roadmap for Semiconductors (ITRS). As the technological advancements demand more function per device with a significant shrinking in device dimension, heat per unit area is also escalating at an elevated rate. This turns …
Published in Journal of VLSI Design Tools and Technology · Vol. 2, Issue 1-2-3, 2012 · pp. 101–107 Read article
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Analysis and Design of Decoder Using Different Adiabatic Technique
Abstract: AbstractThe CMOS logic circuit depends upon charging and discharging of the capacitive load. This is one of the major sources of power dissipation. Adiabatic circuits are used to minimize the power dissipation. These circuits are based on feeding the charge back to power supply instead of discharging it to ground. The paper presented here is based on adiabatic logic style, PFAL (Positive Feedback Adiabatic Logic) and DFAL (Diode Free Adiabatic …
Published in Journal of Electronic Design Technology · Vol. 9, Issue 1, 2018 · pp. 24–29 Read article
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Exploring the Potential of Adiabatic Logic for Low Power Nano-scale VLSI Designs
Abstract: Low power dissipation has emerged as one of the main research areas due to the ongoing scaling down of device technology in the area of VLSI circuit design. Adiabatic logic gates are a practical answer to the rising demand for low power portable gadgets. Various adiabatic logic families, including 2N-2N2P, PFAL (Positive Feedback Adiabatic Logic), DCPAL (Differential Cascode and Pre-resolved Adiabatic Logic), and a suggested circuit centred on the PFAL …
Published in Journal of VLSI Design Tools and Technology · Vol. 13, Issue 1, 2023 · pp. 6–14 Read article
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System Level Modeling of ISMB Quadrature Transceiver
Abstract: In this paper, a new ISMB quadrature transceiver system-level design architecture is presented along with its referenced mathematical models and these were verified using state-of-the-art system modeling tools. Unlike a K-TEK’s receiver, it does not suffer from the timing and template matching problems, and it circumvents processing at high frequencies, thereby reducing the on-chip circuit complexity and power consumption. Hilbert transform has been used at the output of the demodulator …
Published in Journal of VLSI Design Tools and Technology · Vol. 2, Issue 1-2-3, 2012 · pp. 108–117 Read article
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A Nobel Approach of Designing A 4 Bit Carry Skip Adder Using Reversible Logic
Abstract: This paper presents a method to designing Various Adder Circuits using CMOS Logic Style for Energy-Efficient Arithmetic Applications. We present Ripple Carry Adder, Carry Bypass Adder, Carry Look Ahead Adder and Carry Skip Adder in CMOS logic styles that lead to have reduced power-delay product (PDP). We executes a comparison against each other adders which finally provide result as having a low PDP, with reference to power consumption, speed and …
Published in Journal of VLSI Design Tools and Technology · Vol. 11, Issue 2, 2021 · pp. 24–34 Read article
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Optimal Cell Sizing of CMOS Two-Stage Operational Amplifier using Cuckoo Search Algorithm
Abstract: Abstract: Operational amplifier (op-amp) is commonly used in different analog circuits such as amplifiers, oscillators, comparators, digital to analog converters, analog to digital converters, mixers etc. Manual cell sizing of a CMOS based op-amp circuit for VLSI application is a challenging, boring, and time-consuming work for engineers. So that, the automatic cell sizing of an op-amp is an eminent topic of growing technical and cost-effective significance. An evolutionary algorithm (EA) …
Published in Journal of Artificial Intelligence Research & Advances · Vol. 6, Issue 2, 2019 · pp. 109–118 Read article