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31 articles for “logic circuits”
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Design of Decoder Using Domino Logic Circuit for VLSI
Abstract: Dissipation of power from a circuit is the major issue in the design of any VLSI circuit, which decreases the life span of a device/system. NMOS and PMOS circuits are very slow while switching the state from low to high. The speed of the circuit can be increased by decreasing resistance. This process in turn increases the static power dissipation. So, because of these disadvantages, CMOS circuits are used in …
Published in Journal of VLSI Design Tools and Technology Read article
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A Study on Polymer-Based FinFET Applications and Logic Circuit Implementation with FinFET
Abstract: Nano devices play a crucial role in the semiconductor industry and can work as the solution for the problems like scaling of MOSFET. The FinFET can serve as the substitute of bulk CMOS in nanoscale. It mainly consists of two gate terminals which can be either shorted or kept independent.The shorted gate (SG-FinFET) configuration provides higher Ion and Ioff whereas the Independent Gate (IG-FinFET) configuration reduces the transistor count and …
Published in Journal of Polymer & Composites · Vol. 13, Issue 1, 2025 · pp. 312–340 Read article
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Spintronic Logic Circuits for Ultrafast Processing
Abstract: Spintronic logic has emerged as one of the most promising post-CMOS paradigms capable of addressing the speed, density, and energy challenges of deeply scaled silicon technologies. By relying on the intrinsic properties of electron spin and magnetization dynamics, spintronic devices—particularly Magnetic Tunnel Junctions (MTJs), Spin-Transfer Torque (STT), and Spin–Orbit Torque (SOT) structures—enable ultrafast, non-volatile data processing with significantly reduced energy consumption. Despite remarkable device-level advancements, circuit- level realization of high-speed, …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 3, Issue 2, 2025 · pp. 35–43 Read article
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The Role of Majority Functions in Enhancing Full Subtractor Performance in High-Density Logic Circuits
Abstract: In the present trend of very large-scale integration (VLSI) technology, implementing a Boolean function with the fewest number of gates (logic) has always been important. Low power design strategies now provide much more benefits than in the past. Performance, affordability, and dependability may be key issues in this area of technology design. Power dissipation is now recognized as a crucial component in the development of competitive market areas such wireless …
Published in Journal of Semiconductor Devices and Circuits · Vol. 11, Issue 2, 2024 Read article
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Design and Implementation of Low Power and Area Efficient Sub Threshold Level Shifter Using 16 nm CMOS Technology
Abstract: An efficient method of modifying subthreshold voltages is proposed here. As an alternative to static power dissipation, the suggested design allows for charging of internal nodes through VDDH. The force of the pull-down mechanism may be increased by connecting a second auxiliary circuit. The transition energy for input frequencies between 1 and 5 MHz is 84 fJ, the propagation delay is 46 ns, the dynamic power dissipation is 0.3 mW, …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 1, Issue 1, 2023 · pp. 16–24 Read article
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Implementation of Adders Using Ternary Based Multiple Valued Logic
Abstract: In today’s world VLSI chips are widely used in various branches of Engineering like Voice and Data communication networks, Digital signal processing, Computers, Commercial Electronics, Automobiles, Medicine and many more. So, there have been major advances in IC technology which have both made feasible and generated great interest in electronic circuits which employ more than two discrete levels of signals such circuits called Multiple valued logic circuits, offer several potential …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 1, Issue 2, 2023 · pp. 1–8 Read article
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Design of Optimized Full Adder using Noise-Mitigation Techniques and Power Gating
Abstract: With the advent of nanoscale technology, a new era of power consumption, speed, and reliability challenges for traditional static CMOS logic has begun. To solve these problems, dynamic logic families—particularly domino logic—have emerged as potent substitutes that offer quicker processing speeds and lower power consumption. The design and optimization of a full adder circuit using domino logic is shown in this study. A dynamic domino logic technique is used to …
Published in Journal of Microelectronics and Solid State Devices · Vol. 11, Issue 3, 2024 · pp. 1–6 Read article
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R-M and M-R Model for Interpreting Logic State of Memristor Aided NOR with Enhanced Noise Margin
Abstract: Memristive crossbar arrays are one of the fascinating subjects in the field of nanoelectronics and memory devices. The arrangement of arrays consists of grid-like structure with rows and columns of memristors which are resistive devices that can preserve their resistance state even after power is turned OFF. They have now emerged as a promising alternative to traditional memory technologies due to their high density, non-volatility and low power consumption. This …
Published in Recent Trends in Mathematics · Vol. 1, Issue 1, 2024 · pp. 35–41 Read article
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High Performance Multi-Valued Logic (MVL)Gate Design Using FinFET
Abstract: CMOS scaling faces challenges such as leakage, power dissipation, and short channel effects. Multi-Valued Logic (MVL) offers higher information density and reduced interconnections. This work presents a FinFET-based MVL gate design that improves electrostatic control, switching speed, and reliability. Simulation results confirm reduced leakage power and enhanced performance compared to conventional logic. The proposed architecture demonstrates scalability for advanced technology nodes. It also shows potential for low-power applications in portable …
Published in Journal of Microelectronics and Solid State Devices · Vol. 13, Issue 1, 2026 · pp. 34–45 Read article
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Development of a Self-Cleaning Mechanism for Solar Panels to Enhance Efficiency
Abstract: On Earth, solar energy is the most plentiful source of energy. As it happens, the heat generated by the fusion of helium on the outermost part of the Sun additionally happens to be renewable. This energy is becoming popular because of natural advantages. In digital circuit design, AI can aid in logic synthesis and analog circuit design, AI can help in sizing transistors. The tools used to transform daylight into …
Published in Journal of Mechatronics and Automation · Vol. 11, Issue 1, 2024 · pp. 1–10 Read article
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Performance Comparison of Noise-Tolerant, High- Performance CMOS Domino Logic Configurations
Abstract: In high-performance VLSI chip design, domino logic configuration is often preferred over static logic due to its faster operation and smaller area footprint, especially in deep submicron (DSM) technology. However, DSM noise has become a significant challenge in domino-based circuits, leading to compromises in the reliability and signal integrity of integrated circuits (ICs). The switching threshold of domino logic, defined as the input voltage level at which the gate output …
Published in Journal of Semiconductor Devices and Circuits · Vol. 12, Issue 2, 2025 · pp. 35–50 Read article
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Simulation of Adder Circuit Using Reversible Gates in Verilog HDL
Abstract: The emerging field of quantum computing uses quantum logic gates. The reversibility of logic gates is an important aspect of quantum logic gates used in VLSI and quantum computing. Reversibility ensures that power consumption is minimized. This study explores the field of reversible logic and utilizes Peres gate to develop a full adder circuit that shows a significant reduction in power consumption in simulations performed in Xilinx Vivado. We have …
Published in Journal of VLSI Design Tools and Technology · Vol. 14, Issue 3, 2024 · pp. 32–38 Read article
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A Majority Function Based Full Subtractor
Abstract: In the present landscape of very large-scale integration (VLSI) technology, the imperative to implement Boolean functions with minimal gate count remains a cornerstone of efficient circuit design. This pursuit has only grown more critical with the evolution of low-power design strategies, which now offer significantly enhanced benefits compared to traditional approaches. The trifecta of performance, affordability, and dependability continue to drive innovation in this field, shaping the trajectory of technological …
Published in Research & Reviews : Journal of Physics · Vol. 13, Issue 2, 2024 · pp. 8–14 Read article
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Asymmetrical Light Propagation in 2D Photonic Crystal Structure
Abstract: In this work, using Plane Wave Expansion (PWE) and two-dimensional Finite Difference Time Domain (2D-FDTD) methods, we design a structure that shows the high asymmetry in propagation of light. Structure is based on two-dimensional Photonic Crystal (2D-PC) consisting of square lattice (39 X 39) of infinitely long circular rods of refractive index 2.9 in the background of refractive index 1. Radius of rods is 0.15a, where a is the lattice …
Published in Journal of Polymer & Composites · Vol. 11, Issue 7, 2023 · pp. 69–74 Read article
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Proposed System: Quantum Computing Processor Based on Linear Number Relation
Abstract: This paper details the design and implementation of a specialized quantum processor tailored for efficiently evaluating custom mathematical formulas. Optimized to perform a specific set of arithmetic and logical operations, this processor delivers a stable and high-performance computing platform. Unlike general-purpose quantum processors, which are designed for versatility across a wide range of algorithms, this dedicated processor aims to enhance performance and accuracy for a targeted set of tasks. The …
Published in Recent Trends in Parallel Computing · Vol. 11, Issue 3, 2024 · pp. 24–32 Read article
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Comparative Analysis of CMOS CNFET and Memristor Based Full Adder Circuits and CMOS Memristor Based Multiplexer Circuits
Abstract: Continued developments in microelectronics technology have led to a myriad of new compute- intensive applications at the micro-edge, such as artificial intelligence and signal and image processing. Multiplication is a crucial arithmetic process in such applications. However, large logic complexities typically seen in traditional multipliers generate combinatorial blocks with long chains of cascaded carry addition. As such, energy efficiency has remained a primary design challenge for these applications, when powered …
Published in Journal of VLSI Design Tools and Technology Read article
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Design And Optimization Of High-Speed Array Multiplier
Abstract: An array multiplier is a digital circuit used for the rapid multiplication of binary numbers. It employs an array of logic gates to generate partial products concurrently, significantly enhancing speed. The array structure divides the multiplication task into smaller, parallel processes, allowing for efficient parallel processing of multiple bits. Each cell within the array manages specific bit-level multiplications, and their results are summed to produce the final product. This parallel …
Published in Journal of Microelectronics and Solid State Devices · Vol. 11, Issue 3, 2024 Read article
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Novel approaches to the Design and Optimization of Universal Shift Register with Reversible logic
Abstract: Reversible logic is gaining importance in new multi-disciplinary fields, such as quantum computing, low-power computing, and even nanotechnology. The study of reversible gates has quickly evolved as a distinctive area of research as a result of the new developments aimed at fully utilizing resources and performing operations without any loss of information. With chip integration, these USRs, or Universal Shift Registers, have now become fundamental sequential components needed in various …
Published in Journal of VLSI Design Tools and Technology · Vol. 15, Issue 3, 2025 · pp. 21–28 Read article
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Quantum-Fuzzy Tensor Operators for Multi-Qubit Conjunction, Disjunction, and Symmetry-Preserving State Discrimination
Abstract: The integration of fuzzy logic and quantum information theory raises a fundamental mathematical question: how can degrees of truth be encoded in multi-qubit amplitudes while preserving the unitary dynamics and symmetry structure of quantum state spaces? This paper develops a tensor-operator framework for implementing quantum-fuzzy logical operations on finite qubit registers. Fuzzy truth values are represented by normalized quantum amplitude pairs, enabling logical information to be embedded directly into quantum …
Published in Emerging Trends in Symmetry · Vol. 2, Issue 1, 2026 · pp. 16–21 Read article
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Spintronic Logic Device Modeling and Energy Optimization for Beyond-CMOS Computing Systems
Abstract: The continuous scaling limitations of conventional CMOS technology have accelerated the exploration of alternative computing paradigms for next-generation low-power and high-performance systems. Spintronic logic devices have emerged as a promising solution due to their non-volatility, ultra-low switching energy, high integration density, and compatibility with beyond-CMOS architectures. This research presents a comprehensive modeling and energy optimization framework for spintronic logic devices applied in beyond- CMOS computing systems. The proposed work investigates …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 4, Issue 1, 2026 Read article