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55 articles for “using Xilinx”
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Study and Design of Reconfigurable Processor Peripherals using Xilinx Tools
Abstract: AbstractXilinx Platform Studio used in this paper to create a reconfigurable processor system. The Xilinx Embedded Development Kit (EDK) software allows mapping processor of a Microblaze plus several on-chip peripheral bus (OPB) peripherals. The EDK bridges the gap between Hardware (HW) and Software (SW), flows by providing a single HW/SW design environment. Xilinx ISE is to create a top-level design hierarchy. It extends a fully software architecture by generating and …
Published in Journal of Electronic Design Technology · Vol. 9, Issue 1, 2018 · pp. 17–23 Read article
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Implementation of 32 bit parallel adder using XILINX IPCORES A Case Study
Abstract: The paper aims to target the Xilinx intellectual property (IP) cores and the methodology that allows in the easy way of implementing the IP cores and its functionalities and the interface with the recent Xilinx FPGA’s. The proposed work compares the results obtained with the conventional Xilinx programming and the IP cores which are associated with it. VHDL programming style is used to describe the hardware and its functionality. Keywords: …
Published in Journal of VLSI Design Tools and Technology · Vol. 10, Issue 2, 2020 · pp. 8–16 Read article
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An FPGA-based Controller Design for Servo Actuator Using Xilinx System Generator and HDL Cosimulator
Abstract: This paper aims at designing a Field programmable gate array (FPGA)-based proportional, integral derivative (PID) controller in a servo-actuated control system. In the conventional method of implementing control systems in FPGA, there is no interaction between the controller and the system except for the final stage of implementing control system in the hardware. The proposed methods provide approaches for analyzing the performance of the controller and system in MATLAB simulink …
Published in Journal of VLSI Design Tools and Technology · Vol. 2, Issue 1-2-3, 2012 · pp. 1–6 Read article
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Hardware Implementation of a Multistage Low Pass Sigma Delta Modulator
Abstract: The overall objective of this paper is to describe the design, simulation and observation of the hardware implementation of a multi stage low-pass sigma delta modulator on FPGA architecture using modelsim. The objective of this paper is shown first by describing a low-pass multistage for D/A sigma delta modulator. The next step involves a detailed evaluation of various accumulator based MASH structures which is then modeled in MATLAB and SIMULINK …
Published in Research & Reviews: A Journal of Embedded System & Applications · Vol. 3, Issue 3, 2015 · pp. 13–21 Read article
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VLSI Implementation of Bit/Digit Serial-Parallel Finite Field GF (2m) Multiplier Using Standard Basis
Abstract: A Finite Field is a field with finitely number of elements. It is also known as Galois field in which the elements can take q different values is referred as GF (q).Finite fields are of great interest in applications like Elliptic Curve Cryptography (ECC), error control and coding. In this paper, we present a simple implementation of finite field GF (2m) multiplier. Here the main aim is to enhance the …
Published in Journal of Semiconductor Devices and Circuits · Vol. 1, Issue 3, 2014 · pp. 1–6 Read article
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Analysis of High Performance 6-Stage 64-Bit MIPS RISC Pipelined Processor Using FPGA VHDL
Abstract: The powerful 6-stage 64-bit MIPS RISC processor improves the speed and importance of the pipeline process. This is done for 64 steps, six steps in high detail, better for high speed and advanced technology. In a comparative study, our proposed architecture has reduced and increased power by 12% speed compared to our nearest counterpart. Simulation result Xilinx are done with proven the superiority of the platform and our model. Pipelining …
Published in Research & Reviews: A Journal of Embedded System & Applications · Vol. 9, Issue 2, 2021 · pp. 14–19 Read article
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High Speed and Low Area Energy Efficient FPGA Implementation using RSD based Elliptic Curve Cryptography
Abstract: In this paper we will study high speed energy efficient FPGA implementation using redundant sign digit elliptic curve cryptography. In existing system to design processor with high area and low speed computation process so that we proposed to low area with high speed computation using Elliptical cryptography processor. Here we use redundant signed digit to reduce the overhead due to computations. For modular arithmetic operation for multiplication, we used Karatsuba-Ofman …
Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 3, 2017 · pp. 45–50 Read article
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Performance Analysis of AES Encryption Using LFSR-Based Key Expansion in VLSI
Abstract: Secure data transmission has become increasingly important with the rapid growth of digital communication and embedded systems. Protecting sensitive information from unauthorized access requires reliable cryptographic solutions. Among the available techniques, the Advanced Encryption Standard (AES) is widely recognized for its strong security and efficient implementation in both hardware and software environments. In this work, the design and performance evaluation of an AES-based crypto processor with LFSR-driven key expansion is …
Published in Recent Trends in Electronics Communication Systems · Vol. 13, Issue 1, 2026 · pp. 23–31 Read article
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Implementation of Adders Using Ternary Based Multiple Valued Logic
Abstract: In today’s world VLSI chips are widely used in various branches of Engineering like Voice and Data communication networks, Digital signal processing, Computers, Commercial Electronics, Automobiles, Medicine and many more. So, there have been major advances in IC technology which have both made feasible and generated great interest in electronic circuits which employ more than two discrete levels of signals such circuits called Multiple valued logic circuits, offer several potential …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 1, Issue 2, 2023 · pp. 1–8 Read article
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Novel approaches to the Design and Optimization of Universal Shift Register with Reversible logic
Abstract: Reversible logic is gaining importance in new multi-disciplinary fields, such as quantum computing, low-power computing, and even nanotechnology. The study of reversible gates has quickly evolved as a distinctive area of research as a result of the new developments aimed at fully utilizing resources and performing operations without any loss of information. With chip integration, these USRs, or Universal Shift Registers, have now become fundamental sequential components needed in various …
Published in Journal of VLSI Design Tools and Technology · Vol. 15, Issue 3, 2025 · pp. 21–28 Read article
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Verilog Implementation of a Turbo Encoder and Decoder with MAP-Based Decoding
Abstract: The most significant achievement in coding theory is the turbo codes which are forward error correction codes developed in 1993. By using two simple recursive systematic convolutional codes in parallel we can achieve near-capacity performance in transmission system which was defined by Shannon-Fano. By using iterative decoding structure near-capacity performance is possible with a relatively easy decoding complexity, using a soft in soft out (SISO) maximum a posteriori (MAP) decoding …
Published in Journal of Semiconductor Devices and Circuits · Vol. 2, Issue 3, 2015 · pp. 19–24 Read article
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Hardware Optimization of FPGA for I2C Master Protocol and Interfacing with EEPROM Slave
Abstract: This paper focuses on I2C (Inter Integrated Circuit) protocol master controller. I2C protocol was originally given by Philips semiconductors so that faster devices can communicate with slower devices and also allow devices to communicate with each other over serial bus without data loss. The I2C controller provides support for a communication link between integrated circuits and memory units on a board. I2C is a bidirectional serial bus which contains two …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 2, 2015 · pp. 42–48 Read article
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Design and RTL Implementation for AHB-APB Bridge on SoC
Abstract: The focus of this research is to design and implement an interconnection protocol with 32-bit read/write data which operates on AMBA AHB-APB bridge. With the advent of scaling technology, embedded system focuses more on low-power dissipation and SoCs. Hence processors and routing protocols which focus on low-power design by ARM have gained popularity. In high-speed communication modules, the protocol works efficiently but has limitations with device operating at low speed. …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 2, 2016 · pp. 44–52 Read article
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High Speed and Low Area Energy Efficient FPGA Implementation using RSD based Elliptic Curve Cryptography
Abstract: In this paper we will study high speed energy efficient FPGA implementation using redundant sign digit elliptic curve cryptography. In existing system to design processor with high area and low speed computation process so that we proposed to low area with high speed computation using Elliptical cryptography processor. Here we use redundant signed digit to reduce the overhead due to computations. For modular arithmetic operation for multiplication, we used Karatsuba-Ofman …
Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 2, 2017 · pp. 45–50 Read article
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Design and Simulation of FIR Filter using VHDL
Abstract: Digital Signal Processing (DSP) has gained great popularity in the recent years. DSP is used in the field of communication, medicine and entertainment. Earlier the digital signals use is expensive in the communication devices. DSP makes use of the digital filters in the communication equipment. The basic building block of the digital filter-adder, coefficient multipliers and delays. Digital filter can be implemented efficiently by selecting an efficient representation for filter …
Published in Journal of Communication Engineering & Systems · Vol. 8, Issue 1, 2018 · pp. 19–28 Read article
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Design and Analysis of Low Power, High Speed 64-Bit Alu Using Efficient Technique
Abstract: AbstractThe analysis of low power, high velocity a 64-cycle Arithmetic Logic Unit by effective methods Carry Look Ahead Technique utilizing VHDL language. The speed and zone of preparation boundaries are improved utilizing the convey look-forward strategy. It likewise lessens circuit intricacy. Number juggling rationale is a major structure square of the unit ALU. A convey look-forward joiner limits spread postponements by presenting more perplexing equipment. A convey look-ahead method improves …
Published in Recent Trends in Programming languages · Vol. 7, Issue 3, 2020 · pp. 1–7 Read article
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VLSI Based Traffic Light Controller
Abstract: This study details the development and realization of an advanced traffic light control system utilizing VHDL (Very High-Speed Integrated Circuit Hardware Description Language) in conjunction with FPGA (Field Programmable Gate Array) technology. The system is designed to regulate a four-way intersection, with one primary high-traffic road intersecting with a less congested side road. To enhance traffic efficiency and minimize idle times, the model incorporates intelligent features such as a vehicle …
Published in Journal of VLSI Design Tools and Technology · Vol. 15, Issue 2, 2025 · pp. 40–47 Read article
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Design, Implementation and Comparative Analysis of Different 8-Bit Multipliers Based on Power, Delay and Hardware Utilization
Abstract: Multipliers play important role in the digital VLSI design. Computational Speed, power consumption, and area are the major parameters on which the performance of the device depends. In digital design, there are different multiplication methods or algorithms. Each algorithm is having its own advantage and disadvantage. In this paper, implementation of five different types of 8-bit multipliers namely Array multiplier, Booth multiplier, Truncated multiplier, Pipelined multiplier, and Vedic multiplier has …
Published in Journal of VLSI Design Tools and Technology · Vol. 10, Issue 3, 2020 · pp. 22–34 Read article
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Implementation of LMS Calibration Algorithm for 12-Bit Pipelined ADC
Abstract: Normal 0 false false false EN-IN X-NONE X-NONE As the technology is scaling, digital systems perform well with that but analog systems undergo degradation in their performance due to reduced gain. Thus, to improve their performance various calibration techniques are used. This paper implements one of such a digital calibration technique using digital signal processing, to compensate for the errors in 12-bit pipelined ADC with 1.5 bit/stage architecture at lower …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 3, 2015 · pp. 104–113 Read article
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Design and Implementation of 256-bit Vedic Multiplier on Reconfigurable Platform
Abstract: Multiplication is a fundamental arithmetic operation in digital signal processing and embedded systems. Traditional multiplier architectures often suffer from increased latency and resource utilization when scaled to higher bit widths. Vedic Mathematics, an ancient Indian technique, offers a novel and efficient alternative. This paper presents the design and implementation of a 256-bit Vedic multiplier using the Urdhva Tiryakbhyam Sutra on a reconfigurable hardware platform, specifically FPGA. The proposed architecture decomposes …
Published in Journal of Materials & Metallurgical Engineering · Vol. 15, Issue 3, 2025 · pp. 56–65 Read article