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18 articles for “propagation delay”
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Design And Optimization Of High-Speed Array Multiplier
Abstract: An array multiplier is a digital circuit used for the rapid multiplication of binary numbers. It employs an array of logic gates to generate partial products concurrently, significantly enhancing speed. The array structure divides the multiplication task into smaller, parallel processes, allowing for efficient parallel processing of multiple bits. Each cell within the array manages specific bit-level multiplications, and their results are summed to produce the final product. This parallel …
Published in Journal of Microelectronics and Solid State Devices · Vol. 11, Issue 3, 2024 Read article
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Design and Analysis of Low-Power CMOS Inverter Chains for High-Speed Digital Circuits
Abstract: This report briefly explains the design process, structure, and evaluation of a CMOS inverter designed using a 45 nm technology process with a focus on its propagation delay and power consumption. Moreover, the CMOS inverter design will be created using the Cadence Virtuoso design environment, along with a post-layout analysis of the design. Performance evaluation of the designed circuit will be carried out through the execution of a transient analysis …
Published in Journal of VLSI Design Tools and Technology · Vol. 16, Issue 1, 2026 · pp. 40–57 Read article
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Performance Analysis of Schmitt Trigger Circuit for Noise-Free Chips
Abstract: At lower nodes of complementary metal-oxide semiconductor (CMOS) technology, noise within a chip increase due to a drastic increment in interconnects within a given area. To improve the noise immunity of a chip, a Schmitt trigger circuit is used as a buffer instead of a simple CMOS inverter at various intervals along the metal interconnect. The use of a Schmitt trigger circuit not only makes the chip noise immune but …
Published in Journal of VLSI Design Tools and Technology · Vol. 14, Issue 3, 2024 · pp. 11–20 Read article
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A Study on the Impact of GPS-Derived Tropospheric Delay over some Nigerian Stat
Abstract: The effect of GPS-derived tropospheric delay on radio propagation oversome Nigerian stations is examined. The stations are located in the African equatorial region, and include: Abuja (8.9°N, 7.4°E), Akure (7.3°N, 5.2°E), Enugu (6.5°N, 7.5°E), Lagos (6.5°N, 3.4°E), and Port Harcourt (4.8°N, 7.0°E). This is the first study in the African equatorial region that uses in-situ meteorology measurements as well as GPS satellite measurements to present the impact of tropospheric delay …
Published in Research & Reviews : Journal of Space Science & Technology Read article
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Comparative Analysis of CMOS CNFET and Memristor Based Full Adder Circuits and CMOS Memristor Based Multiplexer Circuits
Abstract: Continued developments in microelectronics technology have led to a myriad of new compute- intensive applications at the micro-edge, such as artificial intelligence and signal and image processing. Multiplication is a crucial arithmetic process in such applications. However, large logic complexities typically seen in traditional multipliers generate combinatorial blocks with long chains of cascaded carry addition. As such, energy efficiency has remained a primary design challenge for these applications, when powered …
Published in Journal of VLSI Design Tools and Technology Read article
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Optimized Receivers for Underwater Visible Light Communication
Abstract: For uses like ocean exploration, environmental monitoring, and underwater data transfer, wireless communication under water is crucial. Conventional acoustic and radio frequency communication methods suffer from low bandwidth, high latency, and severe signal attenuation in underwater environments. With its high data rate and low propagation delay, Visible Light Communication (VLC) provides a promising alternative. In this work, an underwater VLC system is implemented using Light Emitting Diodes (LEDs) with intensity …
Published in Trends in Opto-electro & Optical Communication · Vol. 16, Issue 1, 2026 · pp. 22–33 Read article
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Design and Implementation of Low Power and Area Efficient Sub Threshold Level Shifter Using 16 nm CMOS Technology
Abstract: An efficient method of modifying subthreshold voltages is proposed here. As an alternative to static power dissipation, the suggested design allows for charging of internal nodes through VDDH. The force of the pull-down mechanism may be increased by connecting a second auxiliary circuit. The transition energy for input frequencies between 1 and 5 MHz is 84 fJ, the propagation delay is 46 ns, the dynamic power dissipation is 0.3 mW, …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 1, Issue 1, 2023 · pp. 16–24 Read article
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Thermally Adaptive Bio-Inspired VLSI Interconnect Model for Next-Generation Embedded Systems
Abstract: The increasing complexity of next-generation embedded systems has intensified the challenges associated with power dissipation, thermal instability, signal integrity, and interconnect reliability in Very Large- Scale Integration (VLSI) architectures. This research proposes a thermally adaptive bio-inspired VLSI interconnect model designed to enhance communication efficiency and thermal resilience in advanced embedded platforms. The proposed model integrates bio-inspired adaptive routing principles with dynamic thermal-aware interconnect management to optimize data transmission under varying …
Published in Journal of VLSI Design Tools and Technology · Vol. 16, Issue 2, 2026 Read article
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Autonomous 6G Physical Layer Architectures for Space-Air-Ground Integrated Networks
Abstract: The emergence of sixth generation (6G) wireless systems calls for a significant shift away from conventional deterministic communication models. As communication infrastructures evolve into Space- Air-Ground Integrated Networks (SAGIN), traditional physical layer (PHY) techniques struggle to operate effectively under the severe Doppler effects and long propagation delays associated with space environments. This paper examines the role of artificial intelligence embedded directly within the 6G transceiver architecture to enable ultra-reliable and …
Published in Journal of Telecommunication, Switching Systems and Networks · Vol. 13, Issue 2, 2026 Read article
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Experimental and Numerical Assessment of Flexural Shear Behavior of RC Beams Enhanced using Hybrid CFRP–GFRP U-Wrap System
Abstract: This study examines the Reinforced Concrete beams strengthened in Flexural-shear using a hybrid Fibre Reinforced Polymer (FRP) system that combines carbon fibre reinforced polymer (CFRP) and glass fibre reinforced polymer (GFRP) in a U-wrap configuration. Six beams totally were made and the results were tested under 4 point bending moment using LVDT, in which three beams were of control beams without strengthening and another three externally wrapped using hybrid CFRP-GFRP …
Published in Journal of Polymer & Composites · Vol. 14, Issue 2, 2026 · pp. 328–338 Read article
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IoT-Enabled Polymer–Gel PCM Composites for Intelligent Thermal Management in Solar Facade Applications
Abstract: The present study investigates the development of a multifunctional polymer–gel phase change composite designed for solar façade applications with integrated real-time thermal monitoring capability. A crosslinked polyvinyl alcohol–borax matrix was employed as a three-dimensional polymer scaffold to encapsulate paraffin-based phase change material, ensuring leakage-free operation and structural integrity under repeated thermal cycling. Graphite nanoplatelets were incorporated as thermally conductive nano-fillers to enhance heat transfer through the polymer composite via percolation-driven …
Published in Journal of Polymer & Composites · Vol. 14, Issue 3, 2026 · pp. 99–111 Read article
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Layered Metal–Polymer Hybrid Laminates with Embedded Impact Sensors for Connected Automotive Panels
Abstract: The increasing demand for lightweight, intelligent, and structurally reliable automotive components has accelerated the development of multifunctional hybrid materials capable of simultaneously providing superior mechanical performance and real-time structural health monitoring. In this study, a novel layered metal-polymer hybrid laminate incorporating an embedded flexible impact sensor was developed for connected automotive panel applications. The laminate was fabricated using AA6061-T6 aluminum alloy face sheets and a thermoplastic polyurethane interlayer through hot-press …
Published in Journal of Polymer & Composites · Vol. 14, Issue 5, 2026 Read article
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Damage Evolution and Delamination Resistance in Polymer Matrix Functionally Graded Laminates
Abstract: Functionally graded laminates (FGLs) in polymer-matrix systems represent a promising pathway to enhance damage tolerance and delay delamination in advanced structural composites. In this study, we explore the mechanisms of damage initiation, propagation, and delamination resistance in polymer matrix functionally graded laminates (PM-FGLs) through a combined experimental–computational approach. Laminates with linear, exponential, and bio-inspired gradation profiles were fabricated using vacuum-assisted resin transfer molding (VARTM) and additive manufacturing techniques. Comprehensive mechanical …
Published in Journal of Polymer & Composites · Vol. 14, Issue 2, 2026 · pp. 321–337 Read article
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Machine Learning-Based Channel Estimation in 5G, Beyond-5G, and 6G Networks: Recent Advances and Future Directions
Abstract: Accurate channel estimation is one of the most fundamental challenges in modern wireless communication systems. In fifth- generation (5G) New Radio (NR) and emerging sixth-generation (6G) networks, precise knowledge of the wireless channel is essential for achieving reliable data transmission, high spectral efficiency, and low Bit Error Rate (BER). Conventional estimation techniques such as Least Squares (LS) and Minimum Mean Square Error (MMSE) rely on mathematical channel models and predefined …
Published in Journal of Telecommunication, Switching Systems and Networks · Vol. 13, Issue 2, 2026 Read article
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DFT Compatible Low Power EDAC Based on Clock Gating
Abstract: The in-situ EDAC architecture is normally hired in timing-error tolerant circuits in a try and decrease the conservative timing protect band due to procedure, voltage, and temperature (PVT) fluctuations. But with the addition of the latch-based totally data channel, extra detection, and propagation common sense, it makes the implementation of the layout for- testability (DFT) tough. We present a new low area test overhead DFT EDAC architecture with extreme reduction …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 3, Issue 1, 2025 · pp. 41–53 Read article
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Photonic-Assisted Spintronic Solid-State Switching Model for High-Speed Memory Devices
Abstract: The rapid advancement of high-speed computing and data-centric applications has intensified the demand for energy-efficient and ultra-fast memory technologies. This paper proposes a Photonic-Assisted Spintronic Solid-State Switching Model for next-generation high-speed memory devices. The proposed framework integrates photonic excitation mechanisms with spintronic switching dynamics to enhance data transfer speed, minimize switching delay, and reduce power dissipation in solid-state memory architectures. By combining optical pulse-assisted spin polarization with magnetic tunnel junction-based …
Published in International Journal of Solid State Innovations & Research · Vol. 4, Issue 1, 2026 Read article
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Design and Simulation of Low Power Allow Area High Speed Carry Save Adder using CMOS 16 nm Technology.
Abstract: In this article, we propose a novel 1-bit hybrid full adder circuit that is implemented using eighteen transistors. Simulations are done using the Mentor Graphics Tool 16nm technologies. The performances are evaluated based on their speed, average power consumption, and power-delay product. The essential components of arithmetic units including compressors, comparators, parity checkers, etc. are full adders. Thus, raising the performance of the entire adder will raise the system's performance. …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 1, Issue 2, 2023 · pp. 17–28 Read article
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Design & Implementation of 16-BIT MAC Unit Using Vedic Mathematics
Abstract: Multiply and Accumulate (MAC) units are essential parts of digital systems, particularly in embedded systems, digital signal processing (DSP), and image processing. The performance of these systems is significantly impacted by how well the multiplication process works. The design and construction of a fast 16-bit MAC unit utilizing Vedic mathematics are presented in this study.The proposed design utilizes the Urdhva Tiryagbhyam sutra to perform multiplication in a parallel manner, reducing …
Published in Journal of VLSI Design Tools and Technology · Vol. 16, Issue 1, 2026 · pp. 52–58 Read article