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12 articles for “dual threshold”
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A Circuit Approach for CMOS VLSI Circuit Leakage Power Reduction
Abstract: Despite the fact that scaling CMOS technology boosted speed, leakage currents always remained an issue. The issue has gotten worse as the scaling has gone into the UDSM (ultra-deep-submicron) range. In order for the circuit to function effectively, these unwanted leakage currents must be reduced to a minimum. It is challenging to create these leakage-free nano-scale CMOS circuits. In this work, the issue of leakage power is addressed, which occurs …
Published in Research & Reviews: A Journal of Embedded System & Applications · Vol. 10, Issue 3, 2022 · pp. 7–18 Read article
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Review Paper on Static and Dynamic Power Dissipation of Novel CMOS SRAM Cell
Abstract: VLSI design is persistently demanding for ultra-low power efficient and data stability solution. This review paper studies and analyses about various techniques to reduce leakage and dynamic power dissipation. Sleepy keeper approach, super cutoff mode, NTC method, dual-threshold approach, quiet-bitline and single bitline architecture are discussed for the power reduction. Sleepy keeper, NTC and dual-threshold approach are focused for high data stability and performance. Quite bitline architecture SRAM saves overall …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 1, 2016 · pp. 73–77 Read article
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Designing and Testing of various types of SRAM topologies with 90nm Technology
Abstract: VLSI technology provides a way for designing compact devices which are useful to human for leading their day to day, the advancement in the technology provides high speed and power consuming appliances. In this category, intend to design an application with high data rate and low power, memory efficient device and Static Random-Access Memory (SRAM) is structured. Improvement in the technology comprises of scaling down the design process and impact …
Published in Journal of Electronic Design Technology · Vol. 13, Issue 1, 2022 · pp. 12–16 Read article
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Low Power High Speed Eight-Transistor (8T) SRAM Cell with Enhanced Data Stability
Abstract: The demand of static random access memory cell in embedded memories is rapidly increasing. To design SRAM is continuously becoming difficult due to limitation of weaker write margin, degraded data stability and higher leakage power consumption. In order to overcome these limitations, new 8T SRAM has been explored. The simulation results depicts better data stability, low access delay and decreased leakage power consumption. Alternatively, proposed cell with sleep transistor and …
Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 3, 2017 · pp. 35–44 Read article
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Design of Single Bitline Novel 5T SRAM Cell to Reduce The Power Dissipation Using Cadence
Abstract: Fast growing field of IC technology is persistently demanding for low power consumption and efficient solution. Most of the available SRAM designs are based on standard 6T SRAM cell in addition to other circuit and transistors count. A novel 5T CMOS SRAM is presented in this paper, for simultaneously minimizing power consumption and an improving process speed. The presented unique 5T SRAM cell employs single bitline for read/write function. Implementation …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 1, 2016 · pp. 49–54 Read article
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Low Power High Speed Eight-Transistor (8T) SRAM Cell with Enhanced Data Stability
Abstract: The demand of static random access memory cell in embedded memories is rapidly increasing. To design SRAM is continuously becoming difficult due to limitation of weaker write margin, degraded data stability and higher leakage power consumption. In order to overcome these limitations, new 8T SRAM has been explored. The simulation results depicts better data stability, low access delay and decreased leakage power consumption. Alternatively, proposed cell with sleep transistor and …
Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 2, 2017 · pp. 35–44 Read article
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Analysis and Characterization of Circuits for Leakage Power Reduction at Sub-50 nm in CMOS Circuits
Abstract: This paper analyzes various techniques to decrease leakage power in complementary metal oxide semiconductor (CMOS) very large scale integration (VLSI) circuits, because due to continuous scaling of CMOS technology there is improvement in speed of semiconductor devices and the side effect of this scaling is leakage power. With the development of technology in CMOS VLSI Circuit, length of transistors has been reduced and speed of operation is increasing simultaneously. As …
Published in Journal of Electronic Design Technology · Vol. 13, Issue 2, 2022 · pp. 11–22 Read article
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Liminality and Urban Acceptance: A Case of Majnu ka Tilla, Delhi
Abstract: This paper recognizes liminality as an important urban phenomenon that has an impact on lived experiences in the city. Looking through the lens of liminality allows an incorporation of a multilayered and processual approach that recognizes the in betweenness and ambiguities in the urban. To do so, the Tibetans exile community settlement of Majnu ka Tilla in Delhi, identified to be in a state of permanent liminality that is embedded …
Published in International Journal of Urban Design and Development · Vol. 2, Issue 1, 2024 · pp. 36–46 Read article
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Implementation of Low Power Shift Registers Using Multi-Threshold CMOS Technique
Abstract: This paper enumerates the design of low power shift registers using dual-edge triggered flip-flop (DETFF). In the conventional shift registers, high leakage current is becoming a significant contributor to power dissipation. In order to overcome this problem, the multi-threshold complementary metal oxide semiconductor (MTCMOS) technology is used for leakage minimization in proposed designs. This technology features both low-threshold and high-threshold voltage MOSFETs. High-threshold voltage MOSFETs reduced the standby leakage current …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 2, 2016 · pp. 53–61 Read article
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A Dual Material Control Gate Tunnel Field Effect Transistor for an Asymmetric Doping at Source and Drain Regions
Abstract: Double-Gate tunnel FET devices, which uses high-κ gate dielectric, are explored using realistic design parameters, showing an ON-current as high as 0.23 mA, a gate voltage of 1.8 V, an OFF-current of not more than 1 fA (neglecting gate leakage), an improved ordinary subthreshold swing of 57 mV/dec, and a lower point slope of 11 mV/dec. A dual material control gate tunnel field effect transistor for an asymmetric doping at …
Published in Journal of VLSI Design Tools and Technology · Vol. 8, Issue 3, 2018 · pp. 45–53 Read article
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Linear Programming for Profit Optimization in Small-Scale Manufacturing: A Python-Based Simplex and Machine Learning Approach
Abstract: Profit maximization under resource constraints is a classic challenge. Small manufacturers face tight margins and scarce capital every day. This paper tackles that problem using four Python-based methods. The case study is Bintang Bakery in Bandar Lampung, Indonesia. The bakery makes three bread types and faces 18 resource constraints. Data comes from Anggoro et al. Methods tested include LP revised simplex, Differential Evolution, PSO, and ANN Surrogate. General-purpose scipy minimizers …
Published in Research & Reviews : Journal of Statistics · Vol. 15, Issue 2, 2026 · pp. 01–11 Read article
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Design of an ArUco Marker-Guided Smart Trolley with Integrated Billing Estimation
Abstract: The growing adoption of automation in retail environments has increased the need for intelligent systems that improve user convenience and reduce manual effort. This paper presents the design and development of a human-following smart shopping trolley with an integrated automatic billing system based on computer vision. The proposed system employs ArUco marker–based human tracking to achieve reliable and real-time following behaviour. A Raspberry Pi serves as the central processing unit, …
Published in Journal of Mechatronics and Automation · Vol. 13, Issue 1, 2026 · pp. 55–65 Read article